Senior FPGA Design Engineer

Role Overview: As a Senior FPGA Design Engineer at Axiado, you have the opportunity to join a leading company in platform security management and ransomware detection for cloud datacenters, 5G infrastructure, and disaggregated compute ecosystems. Your role will involve RTL design, FPGA prototyping, and computer architecture tasks. You will collaborate closely with various teams within the organization and contribute to the design, verification, debug, and system integration processes. Key Responsibilities: - RTL design for FPGA, including IP integration, closing timing, and generating bit streams - Conduct simulation testing - Set up FPGA systems - Validate and debug FPGA systems - Collaborate with the software team to bring up and validate FPGA system products Qualifications: - Hands-on experience with FPGAs and related tools for compile and timing closure - Strong background in RTL design, particularly for FPGAs - Proficiency in integrating IPs and CPUs for FPGA systems - Experience in RTL simulation testing - Ability to bring up and debug software on FPGA systems - Familiarity with PCIe, USB, Ethernet, SPI, with additional knowledge in ESPI, SGPIO, LTPI considered a plus - Self-driven with excellent problem-solving and communication skills - Bachelor's degree in EE/EECS/CS or equivalent; Master's degree preferred - At least 5 years of industrial experience Additional Details: Axiado is dedicated to attracting, developing, and retaining top talent in a diverse and dynamic environment. The company is headquartered in Silicon Valley, providing access to cutting-edge research, technology, and talent. Axiado is focused on building a strong team to secure every node on the internet, prioritizing real-world problem-solving abilities over theoretical knowledge. The company values traits such as persistence, intelligence, curiosity, hard work, continuous learning, and mutual support among its team members.,