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ACL Digital
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Senior Design Verification Engineer

Senior Design Verification Engineer

ACL Digital

5 - 10 years

22 - 37 Lacs

Hyderabad Bengaluru

Posted:1 month ago| Platform:

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Skills Required

SOC Verification system verilog UVM Ip Verification

Work Mode

Hybrid

Job Type

Full Time

Job Description

Senior/ Lead - Design Verification Engineer SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Experience with python or any other scripting language is a plus Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. BSEE/BS Computer Science, Computer Engineering, Electrical Engineering (or equivalent). Good Experience on Semiconductor/VLSI Design verification IP's. Experience with ISO 26262 is plus Leads must have Faultsim experience Z01X tool experience and any equivalent tool Can consider GLS experience for rest of the engineers. Location: Bangalore / Hyderabad Notice Period: Immediate to 60 days. Experience: 4 to 12 Years

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Senior Design Verification Engineer