Senior ASIC RTL Engineer

7 - 12 years

20 - 30 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)

  • Expertise in SoC subsystem/IP design
  • Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
  • In depth knowledge on RTL quality checks (Lint, CDC)
  • Knowledge of synthesis and low power is a plus
  • Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
  • Good understanding of timing concepts
  • Knowledge of one or more of the interface protocols

        a.    PCIe    b.    DDR    c.    Ethernet    d.    I2C, UART, SPI

    Expertise in setting up and using tools like

        a.    Spyglass Lint/CDC    b.    Synopsys DC    c.    Verdi/XcelliumUnderstanding of scripting languages like Make flow, Perl ,shell, python etcUnderstanding of processor architecture and/or ARM debug architecture is a plusAble to help and debug issues for multiple subsystemsAble to create/review design documents for multiple subsystemsAble to support physical design, verification, DFT and SW teams on design queries and reviews

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