Posted:8 hours ago|
Platform:
Work from Office
Full Time
Digital Design Engineer Technical Skills • Must-Have: • Proven experience in RTL coding and RTL integration of sub-blocks into larger components • Strong expertise in RTL linting debug and error/warning fixes using VcSpyglass • Deep knowledge in analyzing and resolving CDC/RDC violations using Questa • Solid understanding of clocking and reset concepts, including synchronization, generation, and division • Nice-to-Have: • Familiarity with memory subsystems, Tensilica DSP cores and/or communication/control peripheral bus systems • Understanding of on-chip interconnect structures such as Arteris FlexNoC and AMBA protocols • Basic knowledge of digital DFT concepts and their integration with functional design • Exposure to RTL synthesis and timing constraints Responsibilities • Design and integration of RTL components for complex digital systems • Perform linting, CDC/RDC analysis, and resolve issues using VcSpyglass and Questa
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