RTL Design Integration and SDC Engineer

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RTL Design, Integration and SDC Engineer

THE ROLE:

The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of RTL integration of IPs, Sub-Systems and SoC. Must also work on SDC development, SDC generation, verification, promotion/demotion and equivalence checking. Co-ordinate with synthesis, sta and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES:

• Main responsibility is to own the RTL integration of the IPs at Sub-system or SoC level including all the connectivity and usage of custom or industry tools.
• Experience with UPD and power domains, clock gating, clock network connectivity as part of the integration.
• Other responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
• Collaborate with IP teams, synthesis, STA and PNR teams to achieve closure.
• Understand duration required, plan and execute as per schedule.
• Debug and resolve technical issues

PREFERRED EXPERIENCE:

• Must have worked with RTL Design, integration for multiple projects or sub-systems.
• Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
• Preferred top level or SOC level experience
• Have handled blocks with complex designs, high frequency clocks and complex clocking
• Complete understanding of timing constraints, low power aspects and concepts of DFT
• Have debug experience to solve issues.
• Interst in AI, Scripting and automation

ACADEMIC CREDENTIALS:

• Bachelors with 5 years of experience or Masters degree with 3 years of experience in Electrical Engineering

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