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Mirafra Technologies
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RTL Architect

RTL Architect

Mirafra Technologies

8 - 15 years

0 Lacs

karnataka

Posted:4 days ago| Platform: Shine logo

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Skills Required

architecture microarchitecture verification synthesis timing closure cpu interpersonal skills timing closure strong understanding of the design convergence cycle ip dependencies management frontend design tasks planning highspeed serial io protocols clock rate compensation fifo implementation gearbox design for data width power gating low power modes bus fabrics coherencenoncoherent noc domains excellent communication skills collaboration skills micro architecture development bus protocols peripherals memory controllers microprocessors chip io design test plans verification synthesis formal verification postsilicon debug

Work Mode

On-site

Job Type

Full Time

Job Description

As an experienced candidate with 8 to 15 years of experience, you will be responsible for the following key aspects: - Strong understanding of the design convergence cycle, including architecture, micro-architecture, Verification, Synthesis, and timing closure. - Expertise in managing IP dependencies and planning front-end design tasks. - Design and development of high-speed serial IO protocols. - Implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, and low power modes. - Desirable experience in CPU, bus fabrics, or coherence/noncoherent NOC domains. Your skills should include: - Excellent communication and interpersonal skills. - Ability to collaborate effectively in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications for this role: - Ability to develop micro-architecture based on specifications. - Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. - Experience with memory controller designs and microprocessors is an advantage. - Knowledge of chip IO design and packaging is beneficial. - Proficient in reviewing high-level test plans and coverage metrics. - Expertise in Design Compiler Synthesis and formal verification using LEC. - Comprehensive understanding of timing closure is mandatory. - Experience in post-silicon bring-up and debugging. No additional details about the company were provided in the job description.,

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RTL Architect