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Principal Engineer SOC STA Lead

Principal Engineer SOC STA Lead

Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Infineon

14 - 18 years

30 - 35 Lacs

bengaluru

Posted:23 hours ago| Platform:

Apply

Skills Required

sta semiconductor timing closure dft soc diversity and inclusion functional testing perl vlsi design physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets.
Job Description

Responsible for leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond).
Ownership of constraints development for functional/test modes at pre and post layout stage.
Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces.
Timing analysis and convergence of large hierarchical design across multiple modes and corners.
Interact with RTL and DFT teams on timing feasibility and performance assessment.
Work closely with physical design team for timing/SI closure

Your Profile

B.Tech or M.Tech relevant work experience and specialization in VLSI design.
Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs.
Experience in low-power synthesis and equivalence checks will be a plus.
Expert user of industry standard tools for timing signoff.
Experience in scripting languages (shell, perl, tcl) and Make flow.
Must be well organized, methodical and detail oriented.

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Principal Engineer SOC STA Lead