PMTS Silicon Design Engineer

Role Overview: At AMD, you will be working as an ASIC Verification Engineer. Your role will involve driving strategies and successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. You will be contributing to the mission of building great products that accelerate next-generation computing experiences, from AI and data centers to PCs, gaming, and embedded systems. Grounded in a culture of innovation and collaboration, you will be part of a team that believes in pushing the limits of innovation to solve the world's most important challenges. Key Responsibilities: - Technically lead a team and work with cross-functional teams, planning inter-locks with dependent teams, preempting risks, and having a plan to mitigate - Develop UVM/OVM and/or Verilog, System Verilog test benches and use simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify high-performance IPs and/or SOC designs - Drive strategies and successful verification execution on high-performance IPs and/or SOC designs - Have a strong understanding of state-of-the-art verification techniques, including assertion and metric-driven verification - Establish the verification methodology, tools, and infrastructure for high-performance IP and/or VLSI designs - Experience with FPGA programming and software is a plus - Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan / VC Formal) are a plus - Experience with gate-level simulation, power-aware verification, reset verification, contention checking is a plus - Prior experience with silicon debug at the tester and board level is a plus Qualification Required: - Bachelor's or Master's degree in computer engineering/Electrical Engineering Additional Details: Benefits offered are described in detail under AMD benefits at a glance. Join AMD to shape the future of AI and beyond, advancing your career in a culture that values innovation and collaboration.,