PMTS Silicon Design Engineer

As a PMTS SILICON DESIGN ENGINEER at AMD, you will play a crucial role in developing and implementing advanced DFT IP and design methodologies for complex SoCs/ASICs. Your deep technical expertise in DFT architecture and strong leadership skills will be essential in driving execution, mentoring engineers, and ensuring high-quality, testable designs. Here's what you will be responsible for: - **Team Leadership & Management** - Lead and mentor a team of DFX engineers, fostering technical excellence, innovation, and collaboration. - Manage project priorities, schedules, and deliverables to meet program milestones. - Recruit, train, and develop engineering talent. - **DFT Strategy & Execution** - Define roadmap and drive DFT methodologies, flows, and best practices for complex CPU/GPU/SoC designs. - Oversee implementation and verification of DFT RTL build, scan insertion, ATPG, BIST, boundary scan, and JTAG. - Ensure seamless integration of DFT architecture into the overall design flow. - **Technical Ownership** - Provide hands-on guidance in DFT tool and flow usage and debug. - Drive innovation in low-power test methodologies, hierarchical DFT, and advanced fault models. - **Cross-Functional Collaboration** - Partner with architecture, RTL design, verification, and physical design teams to ensure DFX requirements are met. - Collaborate with SOC design and product engineering teams on innovative DFT/DFD design solutions. - Interface with foundry and EDA vendors to adopt cutting-edge DFT solutions. In this role, your experience in leading technical and managerial settings, excellent communication skills, and global mindset will be crucial for success. You will be responsible for full design lifecycle of state-of-the-art DFT IP and fostering a collaborative environment for design innovation. The ideal candidate will have a BSEE, MSEE, or equivalent degree, along with a minimum of 15 years of ASIC design or verification experience. Please note that the job location is in Bangalore, India.,