Posted:3 months ago|
Platform:
Work from Office
Full Time
Role Description Expertise in Placement and routing experience is preferred. Well versed in PNR Flows and Optimizing timing constraints. Ability to analyse route ability, critical path timing, congestion optimization etc Familiar on various aspects of Physical Design like Floorplan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence. Working along with any of different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.. THE ROLE The focus of this role is to collaborate with RTL and behavioural Design. Work along with various teams on Timing/ Placement / Floor planning optimization contributing to subsystem/subCHIP/Full chip for high performance complex SOCs Guiding Physical verification and validation teams till tape off. THE PERSON You have a passion for modern, complex processor architecture, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Allegis Group
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