Memory Layout Engineer

We are looking for a highly skilled and experienced Memory Layout Engineer to join our team. As a Memory Layout Engineer, you will be responsible for designing and integrating layouts for advanced memory blocks across leading-edge process technologies. Your role will involve developing and verifying memory compilers with a strong focus on ultra-deep sub-micron layout challenges. Key Responsibilities: Memory Building Block Layout Design: - Designing layouts for essential memory components including Control and Digital logic, Sense amplifiers, Bit-cell arrays, and Decoders. Process Technology Expertise: - Working with advanced process nodes such as 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, and FinFET technologies. Physical Verification: - Developing memory compilers, addressing layout-related issues, and ensuring optimization. - Proficiency in Routing Congestion, Physical Verification in Custom Layout. - Knowledge of verification checks like DRC, LVS, ERC, Antenna, LPE, DFM, etc. - Understanding of analog layout techniques and circuit principles affected by layouts. Tools Experience: - Hands-on experience with industry-standard layout and verification tools in a Linux environment, including Cadence and Mentor EDA tools. Proficiency in VirtuosoXL. Leadership and Communication: - Demonstrated leadership skills to mentor and guide team members in layout execution. - Excellent communication skills and proactive work approach. Qualifications: - BTECH/MTECH - Minimum 3+ years of experience Location: - Bangalore / Hyderabad / Noida This role presents an exciting opportunity to work with cutting-edge technologies and collaborate with a team of experts. If you are passionate about memory layout design and enjoy working in an innovative environment, we encourage you to apply.,