Memory Layout Engineer

Central Business Solutions

3 - 8 years

15 - 30 Lacs

bengaluru

Posted:-1 days ago| Platform:

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Skills Required

rom semiconductor finfet drc vlsi design cmos analog layout memory design lvs dram

Work Mode

Work from Office

Job Type

Full Time

Job Description

The ideal candidate should possess deep expertise in memory layout techniques, design rule compliance, and physical verification methodologies used in sub-3nm technologies.

Required Candidate profile

Strong understanding of SRAM, ROM, and memory bit-cell architectures.Deep knowledge of DRC, LVS, and parasitic extraction flows.Hands-on experience with advanced FinFET process nodes (3nm or less).

Perks and benefits

custom memory layouts on 3nm or lower nodes.

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Central Business Solutions

IT Services and IT Consulting

Newark CA

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Memory Layout Engineer