Lead Engineer - ASIC Verification

Cradlepoint

12 - 17 years

6 - 10 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

wireless asic simulation soc digital signal processing agile test planning simulink matlab uvm

Work Mode

Work from Office

Job Type

Full Time

Job Description

Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements.

Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced verification technologies alongside skilled experts.
Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide.
Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life.
Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere.
An international work environment with opportunities for professional growth and development.
A collaborative and inclusive culture that values diversity and innovation.
A competitive compensation and benefits package.

Required Qualifications:

Bachelor s degree in electrical or computer engineering.
12+ years of industry experience in verification using SystemVerilog and UVM.
Proven track record of leading verification teams of 8+ engineers for minimum 2 years.
Experience in test plan development in cross-team and international cross-site environment
Proficiency in/with:
- architecting and creating new grounds-up random and directed test environments and testcase strategies.
- formal verification for connectivity checks and using assertion-based VIPs.
- architecting and leading implementation of scoreboards, checkers, bus functional models
- AMBA-based designs such as AXI and CHI.
- SystemVerilog Assertions.
Strong experience in low-power design verification.

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