Infra Systems Architect-PE

Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. Infra Systems Architect Infra Systems Architect for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. This position will be responsible for Technical leadership role working with SOC architects, DMs and PDMs from early stages of the project to understand new usecases and feature requirements IP baseline selection, area projections and feature negotiations Convert the requirements to solutions and work with Infra IP development teams to flawlessly implement them Point of contact in Product core and architecture meetings in identifying and solving system level issues. Work with performance projection team to define experiments, analyze data, draw conclusions, identify potential problems and drive solutions Work with SoC, Verification, Physical Design, SoC Floorplan and core teams in identifying optimizations and drive them into products. Point of contact for debugging Post Si issues at system level. Preferred Qualifications 15+ years of experience in SOC/IP architecture, micro-architecture and design. Good understanding of SOC. Possesses expertise in 1 or more of the following technical areas:DDR, Security, access control, Interconnects, SMMU, SOC power management, boot, clock/reset, UBWC, Encryption, ECC Understanding of ARM architecture (Coherency, bus interconnects, Security, arch evolution) Good communication and leadership skills; work with minimal supervision Collaborate with internal (Perf, Design and System team) and external (SoC arch, Client Ips) stakeholders in developing solutions Understanding of traffic patterns and BW of different clients a plus Experience with high-performance and low power micro-architecture concepts Experience with Verilog, logic design principles with timing, area and power implications. Experience with scripting languages like Perl/Python/Java for developing proof of concept of the new ideas. Performance:explore high performance strategies and validate that the micro architecture meets targeted performance. Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI. Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Good Understanding of concurrency, bandwidth, latency and system level aspects Provides direction, mentoring, and leadership from small to medium sized groups. Education Requirements:Bachelor s degree in Electrical Engineering required, Master's or Doctorate preferred