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Functional Verification Engineer

5 - 10 years

7 - 17 Lacs

Hyderabad

Posted:3 months ago| Platform: Naukri logo

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Skills Required

blocklevel Functional Verification System Verilog Testbench gate level simulation SOC Verification UVM Netlist

Work Mode

Hybrid

Job Type

Full Time

Job Description

Functional Verification Engineer AMD Hyderabad Must have hands on experience coding In System Verilog/UVM. Experience developing testbenches for block level or IP level verification. Experience working on subsystem or SoC level would be helpful. Candidate should be proactive in communication. Developing and maintaining block level test benches. Vplan, regression and coverage closure Work on testbenches with real number modelling. Netlist and Gate level simulations. Must be able to work independently to self-manage to deliverable as per the schedules

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www.allegisgroup.com

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Hanover Maryland

10001 Employees

258 Jobs

    Key People

  • Andy Hilger

    President

  • Michele H. Smith

    Chief Financial Officer

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