Full Chip Physical Integration and CAD Engineer, Silicon

Google

10 - 14 years

0 Lacs

karnataka

Posted:1 week ago| Platform: Shine logo

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Skills Required

timing closure performance improvement synthesis static timing analysis physical verification rtl2gds asic mixed signal chips cad flow physical design integration power convergence physical convergence physical design methodologies automation scripts power improvement area improvement cad methodology place route pdn electrical checks

Work Mode

On-site

Job Type

Full Time

Job Description

Role Overview: As a member of the team, you will be part of a group dedicated to pushing boundaries and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will play a key role in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration for products loved by millions worldwide. Key Responsibilities: - Develop all aspects of RTL2GDS for ASIC/Mixed signal chips. - Take complete ownership of physical design integration and CAD flow for Mixed signal chip development. - Drive the closure of timing and power/Physical convergence of the design. - Contribute to physical design methodologies and automation scripts for various implementation steps. - Define and implement innovative schemes to improve Performance, Power, Area (PPA) and CAD methodology. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 10 years of experience in ASIC physical design flows and methodologies in advanced process nodes. - Experience in synthesis, Place and route (PnR), sign-off convergence including Static timing analysis (STA), PDN, electrical checks, and physical verification.,

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