4 Rtl2Gds Jobs

The custom silicon design team at Microsoft is currently working on developing advanced chips with top-notch performance in the industry. We are seeking highly skilled individuals to join our Physical Design team and contribute to building a world-class team and methodology. The team's responsibilities cover various aspects including DFT, full RTL2GDS, and signoff. If you are a motivated self-starter with the necessary skills to thrive in this environment, we are excited to hear from you! As a Physical Design Engineering Director, your primary role will involve leading a team in defining and implementing methodologies to achieve optimal performance, power, and area (PPA) for AI system-on-chips (SOCs). This will entail optimizing technology, libraries, physical design, RTL design, and architecture. You will also be tasked with developing and executing an auto-convergence methodology to enhance resource efficiency and decrease turnaround time. Your focus will be on fostering innovation and efficiency in the physical design process to ensure that the AI SOCs meet the highest standards of performance and efficiency. The ideal candidate is expected to work effectively with minimal guidance, possess a keen eye for detail, and provide clear updates on progress, issues, and risks to the management team. Some travel may be required as part of the role. Required Qualifications: - Bachelor's or master's degree in electrical or computer engineering or a related field with a minimum of 15 years of experience - Hands-on experience in tapeouts of complex ASICs using cutting-edge technology Preferred Qualifications: - Proficiency in the physical design flow and methodology, process technology and Library, comprehensive Power-perf analysis, projection, and optimization - Demonstrated track record in developing and implementing methodologies for PPA enhancements - Expertise in AI to develop capabilities for enhancing efficiency If you meet the required qualifications and are excited about the opportunity to contribute to the development of high-performance chips at Microsoft, we encourage you to apply and be part of our dynamic team.,

NVIDIA is continuously reinventing itself, with a rich history that includes inventing the GPU, which sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. The current global boom in artificial intelligence research demands highly scalable and massively parallel computation horsepower, a challenge where NVIDIA GPUs excel. As a part of NVIDIA, you will be joining a dynamic team focused on tackling difficult global challenges and amplifying human creativity and intelligence. The diverse and supportive environment at NVIDIA encourages everyone to strive for excellence and make a lasting impact on the world. NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. In this role, you will contribute to the development of high-speed communication devices, ensuring the highest throughput and lowest latency for AI platforms. You will work on designing innovative large-scale chips and collaborate in a professional environment where your contributions matter. Key Responsibilities: - Lead full chip and/or chiplet level STA convergence from initial stages to signoff. - Contribute to top-level floor plan and clock planning. - Optimize CAD signoff flows and methodologies. - Integrate digital partitions and analog IPs timing, provide feedback to PD/RTL, and drive convergence. - Collaborate closely with logic design and DFT engineers to define and implement constraints for various work modes efficiently. Requirements: - B.Sc./M.Sc. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools (e.g., Synopsys, Cadence). - Hands-on experience with STA using Synopsis Primetime. - Strong understanding of timing concepts and a collaborative team player. At NVIDIA, we have a team of forward-thinking individuals who are passionate about pushing boundaries. If you are a creative engineer who enjoys challenges and is ready to grow professionally, come be a part of our industry-leading physical design team. JR1995153,

Qualcomm India Private Limited is seeking a talented Hardware Engineer to join their Engineering Group under the Hardware Engineering division. As a part of Qualcomm, a leading technology innovator, you will play a crucial role in designing, optimizing, and testing electronic systems to contribute to the development of cutting-edge, world-class products. Collaborating with cross-functional teams, you will work towards creating solutions that meet performance requirements and drive digital transformation in the smart, connected future. To qualify for this position, you should hold a Bachelor's or Master's degree from a prestigious institute and possess a minimum of 6 to 10 years of experience in physical design within product-based companies. The ideal candidate will have proven expertise in managing complex subsystems and small teams, along with proficiency in RTL2GDS, including Floorplan, place and route (PnR), and sign-off convergence. In this role, you will be responsible for meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems and System on Chips (SoCs), as well as low power design implementation. Your tasks will include working on multiple technology nodes in advanced processes, ensuring power gating, and driving improvements in PPA through automation. Additionally, you will be expected to lead a small team for project execution and achieving PPA targets. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you may contact Qualcomm via email at disability-accommodations@qualcomm.com or through their toll-free number. As an employee of Qualcomm, you are expected to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this exciting opportunity, please reach out to Qualcomm Careers.,

Seeking a highly experienced Physical Design Methodology/CAD manager to lead/build a team in Bangalore, India. Key Responsibilities Looking for someone with a blend of technical expertise and strong management skills Experience managing/building a team and ability to manage timelines and multiple on-going projects Expertise in PDK enablement and physical design concepts Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Functional Knowledge Demonstrates comprehensive understanding of concepts and principles within own job family and knowledge of other related job families Business Expertise Applies in-depth understanding of how own discipline integrates within the segment/function Leadership Manages multiple related teams, sets organizational priorities and allocates resources Problem Solving Identifies and resolves complex technical, operational and organizational problems Impact Impacts the business results of a team or area by supporting and funding of projects, products, services and/or technologies and developing policies and plansGuided by business unit, department or sub-functional business plans interpersonal Skills Influences others internally and externally, including senior management.