Freelance HBM Verification Engineer (SystemVerilog/UVM | SoC Verification)

Company Description

ThreatXIntel is a cybersecurity startup specializing in delivering customized, cost-effective solutions to protect businesses and organizations from cyber threats. Our team of experienced professionals offers services such as cloud security, web and mobile security testing, DevSecOps, and vulnerability assessments. We are committed to providing high-quality security services tailored to the needs of startups and small businesses, ensuring digital protection and peace of mind for our clients. At ThreatXIntel, we adopt a proactive approach by continuously monitoring and testing digital environments to safeguard against potential vulnerabilities.

Role Description

We are looking for an experienced Freelance HBM Verification Engineer to support SoC and system-level verification for high-performance semiconductor designs. The consultant will work closely with architecture and design teams to develop, integrate, and validate advanced verification environments with a focus on HBM, PCIe, Ethernet, D2D, and high-speed interconnects.

This role aligns with Marvell-style verification flows and requires strong hands-on experience in SystemVerilog and UVM, along with system-level debug capabilities.

Job Responsibilities

• Develop and execute SystemVerilog UVM-based testbenches for SoC and system-level verification
• Integrate and customize VIP components including PCIe, HBM, Ethernet, and D2D
• Create verification components, sequences, scoreboards, assertions, and coverage models
• Perform C-based verification including driver-level validation and system bring-up support
• Debug RTL and testbench issues using industry-standard tools and waveforms
• Automate verification flows and infrastructure using Python, Perl, or Shell scripting
• Work with design and architecture teams to ensure verification completeness
• Contribute to verification plans, coverage closure, and release-ready environments

Required Skills

• Strong hands-on experience with SystemVerilog and UVM methodology
• Experience in SoC or system-level verification
• Scripting skills in Python, Perl, or Unix Shell
• Experience in C-based verification
• Testbench architecture and VIP integration experience
• Strong debugging and problem-solving skills
• Knowledge of PCIe, HBM, Ethernet, or D2D is an advantage