405 Floor Planning Jobs - Page 13

Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years What would you do? "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for? " Agility for quick learning Ability to work well in a team Process-orientation Written and verbal communication Network fundamentals Understanding all the networking devicesRouters, switches, etc. IP connectivity, access, addressing, and services Network security fundamentals Installation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business Networks Excellent Communication Problem Solving Skills Flexibility Teamwork Experience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: " In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shifts Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the output Manage client s optical network, manage alarms and faults in a multi-vendor environment, and Tracking of all work in ticketing system network interconnects with internal and external network operators Track and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providers Manage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary. Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacement Read/Parse vendor notifications and translate to Clients Production Change Request (PCR s) Look up affected circuits to include them in change request Escalate any emergency change requests for immediate review and scheduling Navigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

Long Description Annual maintenance contract preparation and preventive maintenance of QC and IPQA instrument as per approved procedure. Breakdown handling of QC and IPQA instrument as per approved procedure. Upkeep the records of preventive maintenance and breakdown in SAP. Qualification of new instruments and SOP preparation. To participate in failure investigation related to malfunctions. To impart training to the analysts for instruments maintenance and troubleshooting. Co-ordination with vendor service engineer of service /breakdown related activities. To maintain GMP in QC laboratory, Real time documentation. Computer system validation of laboratory instruments. Execution and implementation of quality system in laboratory. Taking part in internal calibration, out-side calibration and reviewing calibration data. Taking part in instrument cleaning maintain & Maintenance of all laboratories indents. QAMS, Caliber-e-log related activities SAP Bill & invoice clearance PO & PR related activity software handling EDMS ,SAP, caliber E log, QAMS, LIMS. etc. Competencies Innovation & Creativity Result Orientation Collaboration Customer Centricity Developing Talent Stakeholder Management Strategic Agility Process Excellence Education Graduation in Mechanical Engineering Work Experience 7 to 8 Years of experience in Quality Control as Instrument Engineer

JD- VM Design Manager-Titan Company Job Title: VM Design Manager Location: [E-city, Phase 1, Bengaluru] Company: Titan Company Limited Job Category : Watches & Wearables-Marketing About Titan: At Titan, we believe in redefining the ordinary. As a Tata Group company, we take pride in being pioneers across categorieswatches, jewellery, eyewear, fragrances, and more. With a deep-rooted culture of innovation and people-first values, our journey is shaped by purpose, integrity, and excellence. We are currently seeking a highly skilled and creative VM Design Manager to join our team at Titan. As a leading company in the watches and wearables industry, we are dedicated to delivering exceptional products and experiences to our customers. Responsibilities: - Develop and implement innovative visual merchandising strategies for our watches and wearables products. - Collaborate with cross-functional teams to create captivating in-store displays and window designs that align with our brand image. - Stay up-to-date with industry trends and competitor analysis to continuously enhance our visual merchandising efforts. - Conduct regular store visits to evaluate the effectiveness of visual merchandising displays and make necessary adjustments. - Work closely with marketing and sales teams to understand product launches and promotional campaigns, and incorporate them into the VM design strategy. - Maintain a strong understanding of our target audience and their preferences to create visually appealing displays that drive customer engagement and sales. Work Experience Requirements: - Bachelor's degree in Visual Merchandising, Design, or a related field. - Proven experience in VM design within the watches and wearables industry. - Strong creative and conceptual thinking abilities. - Proficiency in design software such as Adobe Creative Suite and corel draw - Excellent leadership and team management skills. - Exceptional attention to detail and ability to multitask in a fast-paced environment. - Strong communication and interpersonal skills. Why Join Titan? Be part of a brand that values creativity, curiosity, and purpose. Work alongside industry leaders and visionary thinkers. ¢ Enjoy a people-centric culture where innovation is celebrated. ¢ Build your career with learning, growth, and leadership opportunities.

Category Engineering Hire Type Employee Job ID 10503 Remote Eligible No Date Posted 08/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies. You thrive in dynamic environments and possess a strong problem-solving aptitude. With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development. You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills. Your commitment to diversity and inclusion aligns with Synopsys values, and you are eager to work in an environment that welcomes all perspectives. What You ll Be Doing: Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You ll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation. Who You Are: Detail-oriented with excellent problem-solving skills. Collaborative and able to foster accountability and ownership. Strong written, verbal communication, and interpersonal skills. Committed to diversity and inclusion

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible„¢ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

1. Lead High Performance ARM Core Hardening Job Title: Lead Engineer ARM Core Hardening Location: BLR/Hyd Experience: 812 years Technology Node: 5nm/3nm/2nm FinFET/GAA Reports To: Director/Technical Manager SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster). Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy. Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff. Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization. Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture. Interface with foundry and EDA vendors for process tech enablement and tool issues. Technical Skills: Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache). Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem. Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS. Experience with UPF-based low power flows and Conformal Low Power (CLP) verification. Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement). Familiar with physical architecture trade-offs (voltage islands, power domains, channel management). Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores. Experience taping out at 5nm or lower is mandatory. --- 2. Engineer ARM Core Hardening Job Title: Physical Design Engineer ARM Core Hardening Location: BLR/Hyd Experience: 38 years Technology Node: 5nm/3nm/2nm FinFET/GAA Key Responsibilities: Implement physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic. Perform static timing analysis, IR/EM validation, and physical verification. Optimize for frequency, leakage, and area within power and thermal budgets. Support integration of hardened cores into SoC top-level environment. Technical Skills: Good understanding of ARM core architecture and pipeline structure. Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk). Experience in UPF flows, CPF/UPF constraints, and low-power verification tools. Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs. Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC. Familiar with scripting (TCL, Python, Perl) to automate flows and reports. Work Experience Lead High Performance ARM Core Hardening Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP. Worked with multi-core cluster hardening and coherent interconnects (e. g. , CMN-600). Experience with RTL-based performance modeling and correlation with implementation ARM Core Engineer: ARM POP usage experience. Previous tapeout at \u22647nm. Exposure to hierarchical and multi-voltage designs. Familiarity with advanced floorplanning constraints for multi-core clusters.

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Bangalore Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background in Physical design, physical verification at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What Youll Be Doing: * Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * Physical verification, DRC, LVS, PERC, ERC, ESD, EM and Antenna cleaning. *Co-work with Place & Route team to resolve full chip/IP/block level layout integration issues to drive Physical Verification *Coordinates with internal IP owners on IP related issues. *Coordinates with Manufacturing Team on DRC related issues. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. * Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation in Physical verification and signoff design methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience. Strong Physical verification and signoff experience. Experience in DRC, LVS, DFM, ANT, ERC, ESD, EM and PERC cleaning is mandatory. Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC & ICV Sound understanding of Physical design, Physical verification and signoff concepts. Work with various implementation team to drive full-chip/block level/IP level Physical Verification Sign-off closure in (DRC, LVS, ANT, ERC, ESD, PERC, EM) for tape-out. Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Proven track record of successful physical verification closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...) Exposure to Floorplan & PnR flows and tools such as ICC2/FC/Innovus are added advantage. Good understanding of reliability physics including EM, ESD, crosstalk, shielding, latchup and deep sun-micron challenges. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providing physical verification and signoff solutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals.

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP FI S/4HANA Accounting Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will be involved in designing, building, and configuring applications to meet business process and application requirements. Your typical day will revolve around creating innovative solutions to address specific business needs and ensuring seamless application functionality. Roles & Responsibilities:- Liaising with clients to gather necessary requirements and resolve GST-related queries.- Configuring and maintaining GST settings in SAP, including TDS, E-invoice, and other tax-related modules.- Configuring and Testing of GST returns (Document compliance Reporting), To ensure compliance with GST laws and regulations.- Proficient in implementing and handeling third party integration- Join Cluster Tax team, focusing on localization and deployment- he/she will need to have experience in/with SAP tax reporting or tax determination- he/she will support tax localization requirements during the full project lifecycle.- he/she will review build demos and test results against design/- he/she will support country users in organizational change activities and ensure country users know & act on their responsibilities- he/she will perform cutover and hypercare activities- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Lead the team in implementing best practices for SAP FI S/4HANA Accounting- Conduct regular code reviews and ensure adherence to coding standards- Stay updated with the latest trends in SAP FI S/4HANA Accounting and provide training to team members Professional & Technical Skills: - Strong knowledge of GST laws and regulations.- Proficiency in SAP FICO with experience in end-to-end implementations.- SAP Experience in baseline configuration for GST India in SAP. Experience in SAP FI, MM, and SD.- Must To Have Skills: Proficiency in SAP FI S/4HANA Accounting- Strong understanding of financial accounting principles- Experience in configuring and customizing SAP FI modules- Knowledge of integration with other SAP modules- Hands-on experience in SAP implementation projects- SAP Tax Accounting- SAP S/4HANA Finance- SAP Tax reporting- SAP Tax determination- SAP ARC/DRC is a plus Additional Information:- The candidate should have a minimum of 7.5 years of experience in SAP FI S/4HANA Accounting- This position is based at our Hyderabad office- A 15 years full-time education is required Qualification 15 years full time education

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc We re doing work that matters. Help us solve what others can t.

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Chennai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Kolkata Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Kolkata Work Locations: Salt Lake (City Centre Mall) Park Street (Opposite The Park Hotel) New Town (Axis Mall) Howrah (Avani Riverside Mall) Gariahat (Near Mukti World Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend opportunity Experience working with a reputed restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Mumbai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Mumbai Work Locations: Andheri West (Infinity Mall) Lower Parel (High Street Phoenix Mall) Thane (Viviana Mall) Malad (Inorbit Mall) Vashi (Raghuleela Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

Primary & Mandatory Skill: Python, Docker/Kubernetes Level: SA Client Round (Yes/ No): No Location Constraint if any : No Shift timing: 2-11pm JD: Good hands in Python scripting Experience in Docker & Kubernetes

SENIOR SILICON DESIGN ENGINEER ASIC Physical Design Engineer THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Provide technical support to other teams PREFERRED EXPERIENCE: 5years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

**Job Summary:** We are looking for an experienced and results-driven IC Physical Design Engineer with 5+ years of hands-on experience in digital backend implementation of complex SoCs or ASICs. In this role, you will lead or contribute significantly to block-level and full-chip physical design, timing closure, and sign-off processes in advanced technology nodes. You will work cross-functionally with RTL, DFT, verification, and packaging teams to deliver high-quality silicon on aggressive schedules. **Key Responsibilities:** + Lead physical implementation of blocks and/or full chip through all stages: floorplanning, power planning, placement, CTS, routing, and sign-off. + Drive timing closure using static timing analysis (STA) and optimization techniques for PPA (Power, Performance, Area). + Own physical verification (LVS, DRC, Antenna, ERC) and ECO implementation. + Perform IR/EM analysis, noise checks, and low power verification (UPF/CPF-based). + Interface with RTL, DFT, and verification teams to resolve cross-functional issues and ensure successful tape-out. + Guide junior engineers and review their work to maintain high quality and consistency. + Develop automation scripts to streamline physical design tasks using TCL, Python, or Perl. Collaborate with CAD/Methodology teams to enhance \#LI-RT1 **More details about our company benefits can be found here:** https: / / www.onsemi.com / careers / career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

Primary/ Mandatory skills : Extensive experience in “Chef IT Automation” Secondary skills : Good knowledge and experience in DevOps Level: SA RR : Maintain a consistent terraform script when compared to existing cloud resources Chef version update: version 14 to version 18 Crowdstrike, Qualys and Splunk integration for Ecommerce workloads Packer AMI creation for Windows Core and CentOS Stream 9 Terraform version update Collaborate with DB team for “CentOS version + DB version” update project Test every change made. Work with DevOps, SRE and development teams for testing. Document and publish the changes, and projects undertaken. Client Round (Yes/ No): Yes Location Constraint if any : No Constraints Shift timing: IST 1330Hrs – 2330Hrs

Key Responsibilities: Lead end-to-end physical design flow for complex blocks or full-chip designs. Drive floorplanning, power planning, placement, CTS, routing, and physical verification (DRC, LVS). Optimize timing, power, and area to meet design specifications. Perform hierarchical/flat implementation based on project needs. Work closely with RTL, DFT, STA, and packaging teams. Manage and mentor a team of physical design engineers. Interact with EDA vendors to improve tool flows and resolve tool-related issues. Contribute to methodology improvements and script automation for design efficiency. Required Skills and Qualifications: B.Tech/M.Tech in Electronics/Electrical Engineering or related field. 8+ years of hands-on experience in physical design with deep expertise in block and full-chip implementation. Strong knowledge of EDA tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, RedHawk/Totem, etc. Solid understanding of STA, IR/EM analysis, congestion analysis, and ECO implementation. Experience on advanced nodes (7nm/5nm/3nm) is highly desirable. Prior leadership or team management experience. Strong debugging, scripting (Tcl, Perl, Python), and communication skills.

Responsibilities: * Create detailed layout designs using Virtuoso software. * Perform physical verification through DRC, LVS, ESD checks. * Collaborate with cross-functional teams on floor planning and antenna integration. Annual bonus

P MTS SILICON DESIGN ENGINEER (AECG ASIC PD Architect) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design architecture and flow development for next generation ASICs that meet Engineering, Business and Customer requirements. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Technical Physical Design lead on AECG ASIC solutions, focused on driving the best Power, Performance, Area for customers. Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase. Provide expert guidance to physical design execution teams within AMD and with external partners to drive delivery to customer commitments. Develop technical relationships with broader AMD Design/CAD community and peers. PREFERRED EXPERIENCE: Strong understanding of development of custom ASICs for external customers. Strong background in physical design with exposure to circuit and logic design. Proven track record of delivering SOCs in process technologies 7nm and below. Expert user of P&R, Timing and Physical verification tools from top EDA vendors. Proven expertise in developing physical implementation flows as required. Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design. Experience in leading a small team of high performing individuals. EDUCATION & EXPERIENCE: BS or MS degree in in Electrical Engineering or Computer Science. 16+years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

FELLOW SILICON DESIGN ENGINEER THE ROLE: We are looking for a Fellow-level Engineer to join our team to develop world-class Server products . In this role you will be engaged with Server SOC architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of Server products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology. THE PERSON: You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic. KEY RESPONSIBILITIES: Define and drive PPA uplift methodologies for Server products Develop and deploy end to end power optimization methodology for Physical Design Implementation Define PVT corners, device frequency scaling, frequency targets for next generation Servers in leading foundry technology nodes Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure . Hands-on experience in closing very high-frequency designs Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm Experience driving Physical Implementation methodology Excellent communication skills and strong collaboration across multiple business units PREFERRED EXPERIENCE: 20+ years experience in SOC Physical Design Implementation, Methodology, Signoff and TapeOut In-depth experience and deep conceptual understanding of domains like Full Chip Floorplanning, CTS, PnR, STA, PV, EMIR, Low power design, Logic synthesis, LEC/Formality, VSI, etc. Presentations, Papers and proven innovations, Patents in these domains is a strong plus Forward looking and dependable techincal leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper. Experience working seamlessly across engineering disciplines and geographies to deliver excellent results ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SK5 Benefits offered are described: AMD benefits at a glance .

Video Editing Intern Jaipur (In-office) - Digi Spheres Video Editing Intern Jaipur (In-office) Job Summary: We re seeking a creative and technically skilled Video Editing Intern to bring our content to life. You ll be responsible for editing short-form and long-form content for various platforms. Key Responsibilities: Edit videos, reels, and motion graphics for client campaigns Add music, text, transitions, and other visual effects Optimize content for Instagram, YouTube, and other platforms Collaborate with content creators and strategists for ideation Requirements: Proficiency in Premiere Pro, Final Cut Pro, or CapCut Strong sense of pace, timing, and narrative flow

Job Title: Floor Manager Location: Bandraa (Mumbai) & Sultanpur (Near Chattarpur , Delhi) Job Type: Full-time Industry: Fabrics/Home Furnishings Key Responsibilities: Manage the daily floor operations, ensuring smooth functioning and excellent customer experience. Lead and motivate the team to meet sales targets and maintain high standards of service. Maintain an attractive and organized store layout, ensuring all displays meet brand guidelines. Provide exceptional customer service, handling inquiries and resolving issues promptly. Monitor inventory levels, ensuring adequate stock availability and timely replenishment. Conduct regular training sessions to improve staff performance and product knowledge. Ensure adherence to company policies, safety standards, and operational protocols. Key Skills & Requirements: Presentation: Should be well-groomed, professional, and presentable. Communication: Excellent verbal and written communication skills. Experience: Proven experience in fabrics, home furnishings, or related retail industries. Prior team management or supervisory experience is preferred. Strong organizational and problem-solving skills. Ability to work in a fast-paced, customer-focused environment. Educational Qualifications: Bachelors degree or equivalent experience in Retail Management or a related field is preferred. Why Join Us? Opportunity to work with a reputed brand in the fabrics/home furnishings industry. Growth prospects and professional development. Dynamic and collaborative work environment.