DIGITAL DESIGN VERIFICATION (PHY)

You will be responsible for building and architecting verification environments, preferably from scratch for multiple projects, with 8-15 years of experience in DV. - Write test plans and enhance verification environments. - Comfortably code any portion of a test bench (models, checkers, scoreboards, coverage monitors, etc.). - Develop constraint random DV environments for large ASIC blocks. Qualifications Required: - Must have experience in Verilog/SystemVerilog. - Strong UVM (must) and Specman (is a plus). - Formal verification experience is a plus. - Experience with C++ is a plus. - Experience with Automotive, MIPI PHY standards. - Experience with PCIe and/or networking (Ethernet/PCS) protocol. - Experience with gate-level simulation and debug. - Scripting knowledge in Perl and Python. - Experience with SoC verification. - Good interpersonal and communication skills. - Experience in assertion methodology, emulation/hardware acceleration platforms is a plus. Please note that the company culture encourages a passion for technology solutions impacting businesses, while also supporting personal growth and fulfillment. Working at MarvyLogic will provide you with exposure to various industries and emerging technologies, helping you evolve both professionally and personally.,