The successful candidate will be an integral part of the design team and will have responsibility for all aspects of Digital design capability. These will include system architecture, micro-architecture and circuit realization using RTL design and simulation tools.
The successful candidate will have a proven track record in digital circuit design tasks including architecture, specification, modelling, RTL development and block level verification. Experience of synthesis, timing analysis, back-end extraction, and post layout functional GLS verification would be an advantage but is not necessary. The design engineer in ADI is encouraged to participate in cross company technical initiatives as well as to patent and publish work where possible.
Qualifications
Education and Experience Requirements:
Masters / bachelor s degree in Electronics/Electrical engineering with at least 15+ years experience in digital IC development.
Knowledge of one or more of the following is required
- Expert in Digital design and verification from specification and front-end design through to physical implementation
- Experience working with deep-sub-micron nodes
- Background in micro-architecture, digital design (preferably with multiple clocks), datapath design, design assertions and slow speed peripherals.
- Ability to create state machines, data paths, clock domain crossing logic and arbitration logic
- ASIC design experience is a must including high-speed and low-power(UPF) RTL design.
- Work experience in Ethernet domain is highly desired.
- Experience working with Digital design areas in different technology nodes at both IP and SoC levels
- Proficient coder using Verilog/System verilog and strong debugging skills.
- Expertise in AMBA based bus protocols.
- Strong understanding of clocking/reset concepts is required.
- Hands on experience in linting and CDC tools is a must.
- Experience in timing constraints development and timing closure
- Familiarity with DFT, GLS and physical design methodologies
- Post Silicon debug experience is desirable
- Experience with silicon and software product development and understanding the product development lifecycle
- Experience working with UVM/OVM methodologies
- Knowledge of Communications protocols, and in particular IEEE 802.3 specifications for (100/1G) Ethernet, would be a benefit
- Understanding of analog and mixed-signal circuits and partitioning with digital blocks.
- Knowledge of Digital Signal Processing and algorithmic modelling with tools such as Matlab, and the implementation of efficient RTL code will be an added plus.
- Processor-based SoCs, SystemVerilog, interface protocols, and silicon debug.
- Strong verbal and written communication skills and the ability to communicate with colleagues at remote sites.
- Ability to develop schedules, deliver on time and estimate design performance parameters (like area, speed and power)
- Mentor and coach junior team members / NCGs. (new college Graduates)
- Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe
- A self-starter and works independently with little or no supervision.
- Intelligence, enthusiasm, problem solving, teamwork and a solid work ethic are highly valued.