DFT Lead

As a DFT Engineer/Lead, you will be responsible for various aspects of IP and SoC DFT including DFT Architecture, Spyglass DFT, RTL implementation, Verification, Scan, ATPG, MBIST, Repair implementation, and TOP DFT architecture Design. Your direct responsibilities will include: - Working on various aspects of IP and SoC DFT such as DFT Architecture, Spyglass DFT, RTL implementation, Verification, Scan, and ATPG - SCAN insertion, ATPG, and pattern simulation/debug - MBIST and Repair implementation and verification - TOP DFT architecture Design - ATE vector setup and Yield improvement You must be able to drive the DFT implementation for features like Scan, MBIST, TAP, etc. and have executed at least 3 full SoC end-to-end as a DFT engineer. Qualifications: - Bachelor's in Electrical/Computer Engineering, Computer Science, or related field with 10+ years of relevant experience OR a Master's degree in Electrical/Computer Engineering, Computer Science, or related field with 8+ years of relevant experience - Strong background in ATPG with good experience in SCAN related processes - Previous experience working with manufacturing engineering on pattern delivery and post-silicon support is a definite plus - Experience in architecting the DFT for multiple SoCs, leading team members, and signing off DFT for multiple SoCs Please note that the company values experience, expertise, and a proactive approach to driving DFT implementations for complex SoCs.,