Home
Jobs
Allegis Group logo

Design verification Engineer

5 - 10 years

5 - 15 Lacs

Bengaluru

Posted:2 months ago| Platform: Naukri logo

Apply

Skills Required

Soc Design Design Verification JTAG dft Verdi Version Control UVM System Verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT. 5+ years of Design Verification experience with strong Verilog, System Verilog, C++ and UVM/OVM knowledge Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Ability to come with detailed testplan based on the Arch specs Exposure to DFT concepts such as JTAG, SCAN, memory BIST is an added advantage. Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team and be a proactive member of the team.

More Jobs at Allegis Group

Associate II - Quality Auditor (Claims/Insurance)(N)

Delhi NCR, Gurgaon

1 - 2 yrs
|

INR 2 - 4 Lacs

Quality Auditor - US Healthcare

Gurgaon

1 - 4 yrs
|

INR 1 - 4 Lacs

C++ Developer

Bengaluru

3 - 7 yrs
|

INR 4 - 9 Lacs

Client/Customer Management

Noida

Experience: Not specified

|

INR 1 - 5 Lacs

Mechanical Engineer

Bengaluru

Experience: Not specified

|

INR 1 - 5 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Soc Design Interview Now

My Connections Allegis Group

Download Chrome Extension (See your connection in the Allegis Group )

chrome image
Download Now
Allegis Group
Allegis Group
www.allegisgroup.com

Staffing and Recruiting

Hanover Maryland

10001 Employees

258 Jobs

    Key People

  • Andy Hilger

    President

  • Michele H. Smith

    Chief Financial Officer

RecommendedJobs for You

Allegis Group logo

Design verification Engineer

Allegis Group

Bengaluru