Design Engineering Manager

At Cadence, we are always on the lookout for leaders and innovators who are passionate about making a difference in the world of technology. As a Design Engineering Manager, you will be based in Bangalore and play a crucial role in Cadence's electronic design endeavors. With over 30 years of expertise in computational software, Cadence is dedicated to transforming design ideas into reality through its Intelligent System Design approach, offering a range of software, hardware, and IP solutions for various market applications. Working at Cadence comes with its own set of advantages: - You will have the opportunity to work with cutting-edge technology in an environment that fosters creativity, innovation, and impactful contributions. - Our employee-friendly policies prioritize the well-being and professional development of our team members, offering ample learning opportunities and recognizing individual successes. - The "One Cadence - One Team" culture promotes collaboration across teams to ensure customer success. - There are multiple avenues for learning and development tailored to individual interests and requirements. - You will collaborate with a diverse team of dedicated individuals who strive for excellence every day. In this role, you will join the Post Silicon Physical Layer Electrical Validation team in Bangalore and lead efforts in developing infrastructure for pre-silicon validation and post-silicon validation on Cadence's High-Speed SERDES Test chips. Your responsibilities will include designing the necessary hardware and software architecture for testing the test chips, defining rigorous test plans, executing tests, and generating detailed test reports based on the results. Key Qualifications we are seeking in potential candidates include: Minimum Qualifications: - 6-10 years of experience with a B.Tech degree or 4-8 years with an M.Tech degree in Post-Silicon Physical Layer Electrical Validation. - Profound experience in Physical Layer electrical validation of at least one High-Speed SERDES protocol such as PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO, etc. - Strong hands-on experience with lab equipment like Oscilloscopes, Network Analyzers, Bit Error Rate Testers (BERT), etc. Preferred Qualifications: - Experience in managing small teams and leading post-silicon validation efforts for full projects. - Prior experience in FPGA Design, PCB schematic and layout design, prototyping, and Pre-Silicon IP/SoC Physical Layer Electrical Validation. - Familiarity with Verilog RTL coding, FPGA coding, Labview, Python, C/C++, and TCL. - Experience in conducting hiring interviews and mentoring new team members. - Passion for analog and digital electronic circuit design and signal processing aspects. At Cadence, we are committed to tackling challenges that others can't. Join us in our mission to make a meaningful impact through our work.,