Design Engineering Manager

As a Design Engineering Manager at Cadence, you will be responsible for leading pre-silicon Physical Layer Electrical Validation infrastructure development and post-silicon validation efforts, primarily focusing on Cadence's High-Speed SERDES Test chips. Your role will involve designing the hardware and software architecture required for testing the test chips, defining rigorous test plans, implementing tests, and generating high-quality test reports based on the results. In addition, you will have the opportunity to work on cutting-edge technology and be part of a diverse team dedicated to customer success and innovation. **Key Responsibilities:** - Lead pre-silicon Physical Layer Electrical Validation infrastructure development - Manage post-silicon validation efforts for Cadence's High-Speed SERDES Test chips - Design hardware and software architecture for testing test chips including test PCBs, controlling FPGA platforms, and Labview/python automation - Define test plans to ensure compliance of test chips to Physical Layer Electrical specifications - Implement planned tests and generate high-quality test reports - Utilize lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) for validation **Qualifications Required:** **Minimum Qualifications:** - 6-10 years of experience with Btech or 4-8 years with Mtech in Post-Silicon Physical Layer Electrical Validation - Deep experience in Physical Layer electrical validation of at least one High-Speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO - Strong hands-on experience with lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) **Preferred Qualifications:** - Experience in managing small teams and leading post-silicon validation efforts for at least one full project - 1-2 years of FPGA Design, PCB schematic and layout design & Prototyping experience - Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug - Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL - Experience in conducting hiring interviews and mentoring new hires - Passion for analog and digital electronic circuit design and signal processing aspects At Cadence, you will have the opportunity to work with a passionate and talented team, where employee-friendly policies promote physical and mental well-being, career development, and continuous learning. Join us in solving challenging problems and making an impact in the world of technology.,