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CPU - Processor Verification Engineer – Fabric/On Chip Network

CPU - Processor Verification Engineer – Fabric/On Chip Network

9 - 14 years

|

11 - 16 Lacs

Bengaluru

Posted:2 months ago| Platform:

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Skills Required

continuous integration asic python functional verification unix soc verification c++ soc vhdl sub-system rtl design git axi devops computer architecture linux debugging ahb perl system verilog asic verification c ovm cpu uvm verilog logic design

Work Mode

Work from Office

Job Type

Full Time

Job Description

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verificationplans,environment, testbenches and writing testcasesfor theCacheCoherency TransportInterconnectFabric in IBM Server Processors. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 9+ years of experience in Functional Verification of processors or ASICs. 3+years of experience inthe followingareas Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processorCacheCoherency/Network on Chip/MemoryHierarchyverification. AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabricinterfaceverification or any otherProcessor/SoC coherency transport interconnectfabric verification. Minimum one full life cycle leadership experience of a processor/SoC verification flowwith focus on Coherency Transport Interconnectand/or Network on ChipVerification Good object-oriented programming skills in C++/SystermVerilog, scripting languages like Python/Perl. Verification knowledge inClock domain crossing and reset domaincrossing Knowledge of functional verification methodology likeUVM/OVM Knowledge of HDLs (VHDL/Verilog) Developed testplans and test strategies for IP/unit/block level verificationof Coherency Transport Interconnects Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure.

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