CPU DFT Manager

ACE (All Core Engineering) India is a key innovation hub driving Intel''s cutting-edge design and engineering solutions for next-generation computing platforms. Our team focuses on delivering world-class Core IP, enabling high-performance, energy-efficient products that power the future of computing. At ACE India, you will collaborate with global experts, work on industry-leading technologies, and contribute to shaping the future of semiconductor design. We are looking for an DFT expert to lead the Design-for-Test (DFT) design and verification for X86 CPU cores within ACE India. This role combines deep technical expertise with leadership skills to manage a high-performing team and deliver robust, testable designs for next-generation CPUs.

Key Responsibilities:

DFT Design and Verification:

• Implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using industry-standard tools.
• Drive DFT verification for features such as scan, arrays, and DFD using RTL simulations and emulation.
• Create plans and tests for validating portions of complex microarchitecture using written specs, RTL code, and other test guides.
• Technical Problem Solving: Debug failures to root cause and learn architecture/microarchitecture deeply.

Leadership and Management:

• Collaborate with post-silicon/manufacturing teams on ATE, debugging and resolving issues.
• Manage and technically guide a high-performing DFT team focused on X86 CPU DFT design and validation.
• Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high-quality delivery
• Cross-Functional Collaboration:o Work closely with global stakeholders to address DFT challenges and improve product quality.o Ensure alignment of timelines and deliverables across sites

Required Qualifications:

• 10+ years of experience in DFT domain at IP or SoC level.
• 5+ years of experience managing and leading teams
• Strong knowledge and experience in Spyglass DFT.
• Hands-on skills in implementing JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry
• Expertise in DFT Design and verification using RTL simulations and emulation.
• Good understanding of timing constraints and DFT mode timing analysis.
• Proficiency in RTL coding and shell scripting.
• Experience working with post-silicon/manufacturing teams on ATE, including debugging and issue resolution.
• Experience with X86 CPU architecture and microarchitecture.
• Familiarity with advanced process nodes and hierarchical DFT strategies.
• Strong communication and leadership skills for cross-site collaboration