We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and motivated Physical Design Engineer with a passion for innovation and a proven track record in the semiconductor industry You thrive in dynamic environments and are adept at managing multiple projects simultaneously Your deep understanding of the full design cycle from RTL to GDSII, particularly in advanced FinFET nodes, positions you as a technical driver in your field You possess excellent communication skills, enabling you to effectively collaborate with cross-functional teams and stakeholders Your solid software and scripting skills, combined with your expertise in CAD automation methods, make you an invaluable asset to any project You are autonomous, capable of making timely judgments, and able to handle interruptions with ease, What Youll Be Doing: Driving the physical implementation of high-speed interface IPs and test-chips from SYN to GDS, Utilizing your software and scripting skills to enhance CAD automation methodology for the team Collaborating with multiple functional groups, including front-end, analog and CAD teams, Focusing on advanced SerDes developments, including the latest 112G/224G PAM4 standards, Leading the physical design team to ensure on-time delivery of projects, The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything, Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements, Reducing the risk and time-to-market for differentiated products, Driving technological innovation through advanced SerDes development, Enhancing Synopsys reputation as a leader in chip design and verification, Supporting the company's mission to power the worlds most advanced technologies for chip design and software security, What Youll Need: 10+ years of physical design experience with recent contributions to project tape-outs or IP delivery Strong tcl scripting skills in Place & Route Tools (Fusion Compiler / ICC2 / Others) Understand version control & have experience in one of the version control software (Perforce / Git / Svn / Clearcase) Experience with advanced FinFET nodes, TSMC 7 nanometer or below, Solid understanding of IC design, implementation flows, and methodologies for deep submicron design, Proven track record for technical steering of physical design teams for on-time delivery, Who You Are: Excellent communicator with the ability to engage with peer groups and customers, Autonomous and capable of making timely judgments, Proficient in software and scripting skills (Perl, Tcl, Python), Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs, Able to travel internationally as required, The Team Youll Be A Part Of: You will be part of a collaborative team within the Mixed-Signal IP organization, working closely with front-end, analog, and CAD teams The team focuses on the physical implementation of complex mixed-signal IPs and test-chips across multiple process technologies, with a specific emphasis on advanced high-speed SerDes platforms, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,
