Senior ASIC Design Engineer

HOW YOU WILL CONTRIBUTE AND WHAT YOU WILL LEARN

1. Interacts with RTL designers to understand the flow of work, develops the architecture to automate the flow and then implements the automation to eliminate pain points and errors to de-risk projects.
2. Develop Synthesis flows and run synthesis along side with other designers and provide feedback to designers to improve timing and power.
3. Develops scripts to automate using Python, Perl or other scripting languages.
4. Works as part of a methodology team to develop new CAD/methodologies or flows which improve quality of design, reduce design time and provide consistent and reliable results across users and sites and streamline the process of ASIC development.
5. Identifies input variables, categorizing them as fixed or customizable or user controllable options allowing users to have simplified interaction with the tool flow.
6. Identifies scope for improvement in existing flows and implement those improvements.
7. Work with experts and users across sites to identify new methodologies for development and adoption.
8. Works with EDA tool vendors to identify options available across tools which reduce debug and development effort. Takes the options and make them available in a simplified way to design engineers.
9. Works with EDA tool vendors to evaluate new tools and new features.
Develops flows, take it through a proof-of-concept on a project and release the flow for production use across teams and sites.
10. Makes presentations to teams to ramp users about improvements or new flow development.

Qualifications

1. Hold a Bachelor or masters degree in electrical or computer engineering
2. Have a minimum 2 years of RTL design experience
3. Strong experience in Synthesis, STA and constraints development
4. Strong working experience of Shell, Perl, TCL and other programming/scripting language
5. Strong problem-solving skills
6. Good verbal/written communication skills and teamwork
7. Knowledge of Synopsys Electronic Design Automation (EDA) tools an asset
8. Knowledge of Verilog or System Verilog
9. Knowledge of LSF
10. Knowledge of machine learning and/or neural networks may be an asset