ASIC RTL Designers Lint/CDC

2 - 6 years

0 Lacs

Posted:1 day ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

As an experienced professional with 2-6 years of expertise in micro architecture design and system design using Verilog, SV, or VHDL, you will play a crucial role in this position. Your responsibilities will include: - Utilizing Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. - Demonstrating familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C. - Conducting synthesis, timing analysis using various industry standard tools, and proficiency in TCL and Python scripting. To excel in this role, you should ideally possess a notice period of immediate availability to 1 month. The position is based in BLR/Hyd locations.,

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