ASIC RTL Designers Lint/CDC Sequentia Technologies Pvt Ltd

2.0 - 6.0 years

0 Lacs

karnataka

On-site

As an experienced professional with 2-6 years of expertise in micro architecture design and system design using Verilog, SV, or VHDL, you will play a crucial role in this position. Your responsibilities will include: - Utilizing Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. - Demonstrating familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C. - Conducting synthesis, timing analysis using various industry standard tools, and proficiency in TCL and Python scripting. To excel in this role, you should ideally possess...

Posted 1 month ago

AI Match Score

Apply

ASIC RTL Designers Lint/CDC Sequentia Technologies Pvt Ltd

2.0 - 6.0 years

0 Lacs

karnataka

On-site

The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 mon...

Posted 3 months ago

AI Match Score

Apply

ASIC RTL Design Engineer - Qualcomm

2.0 - 6.0 years

0 Lacs

hyderabad, telangana

On-site

Qualcomm India Private Limited is seeking a talented individual to join their Hardware Engineering team. As a part of the Engineering Group, you will be responsible for ASIC design with a focus on digital front end design. The ideal candidate should hold a PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with 3-5 years of relevant experience in ASIC design. Key responsibilities include RTL coding in Verilog/VHDL/SV for complex designs with multiple clock domains, expertise in bus protocols like AHB, AXI, and NOC designs, and experience in low power design methodology and clock domain crossing designs. Additionally, the candidate should have ...

Posted 3 months ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.