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ASIC RTL Design Lead

9 - 14 years

20 - 25 Lacs

Bengaluru

Posted:3 weeks ago| Platform: Naukri logo

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Skills Required

RTL design C++ ASIC Interpersonal skills DFT Power management System verilog Firmware RTL Design Lead

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Work from Office

Job Type

Full Time

Job Description

Position: ASIC RTL Design Lead (SI90FT RM 3217) Job Description: Innovate, implement, and verify RTL code for complex PHY sub systems dealing with high speed blocks using Verilog/System Verilog knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must. Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution Previous experience with storage systems, protocols, in NAND flash /DRAM controller PHY Basic understanding of PHY system level concepts Experience in PHY architecture, power management and Registers understanding to interact with FW design. Proficient in C, C++, Lint Excellent interpersonal skills and Team Player High level of integrity and commitment to quality and timeliness. Understanding of Hardware Block Diagrams, Schematics Understanding of PHY Architecture document and programming guidelines Understanding of PHY integration guidelines implementation Strong can-do attitude Job Category: Embedded HW_SW Job Type: Full Time Job Location: Bangalore Experience: 9+ YEARS Notice period: 0-30 days

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Sourceright Technologies
Sourceright Technologies
www.sourceright-technologies.com

Technology / Human Resources

Silicon Valley

150 Employees

90 Jobs

    Key People

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    CEO

  • Jane Smith

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