ASIC RTL Design Lead

Modernize Chip Solutions (MCS)

10 - 14 years

0 Lacs

hyderabad telangana

Posted:1 month ago| Platform: Shine logo

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Skills Required

rtl design verilog soc pcie ethernet lint cdc synthesis tcl scripting perl scripting timing analysis subsystem integration usb integration front end flow environment bringup flows formality vclp cdc constraint development signoff

Work Mode

On-site

Job Type

Full Time

Job Description

We are seeking an ASIC RTL Design Lead to join our team in Hyderabad at the earliest. The ideal candidate should possess over 10 years of experience and demonstrate expertise in the following areas: - Proficiency in RTL Design utilizing verilog - Experience in SoC and Subsystem integration, including the integration of peripherals such as PCIE, Ethernet, and USB - Ability to conduct front end flow environment bringup - Strong understanding of Flows, Lint, CDC, Synthesis, Formality, VCLP - Knowledge of tcl or perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff If you meet these requirements and are interested in this opportunity, please send your profile to ratul.chakraborty@modernchipsolutions.com.,

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Modernize Chip Solutions (MCS)

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ASIC RTL Design Lead