Analog Layout Design Engineer with Lower nodes

4 - 6 years

0 Lacs

hyderabad telangana india

Posted:5 days ago| Platform: Linkedin logo

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Skills Required

layout design development signal integration verification lvs drc dfm cadence graphics communication power

Work Mode

On-site

Job Type

Full Time

Job Description

Key Requirements:

  • Experience:

     4 to 6 years (flexible up to 8 years for highly relevant profiles)

  • Location:

     Hyderabad

  • Interview Mode:

     Face-to-Face interviews in Hyderabad

  • Foundry Experience:

     TSMC 5nm/3nm is 

    mandatory

    ; other foundries like Intel, Samsung, GF are acceptable

  • Technical Skills:

  • Design and development of analog, mixed-signal, and custom digital blocks
  • Full-chip level integration support
  • Verification flows: LVS, DRC, DFM, Antenna check, EMIR
  • Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS expertise

  • Education:

     BE or MTech in Electronics/VLSI Engineering

  • Soft Skills:

     Strong communication skills and ability to work independently

  • Additional Advantage:

     Experience with HBM and analog blocks like Regulators, Charge Pumps, Power Management

  • Recent Experience:

     Candidates must have hands-on experience with lower nodes in recent projects



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