Advisory DFT Engineer

2 - 6 years

7 - 11 Lacs

Posted:None| Platform: Naukri logo

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Full Time

Job Description


We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team.As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise
  • Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.
  • Proven expertise in analysing and resolving DRCs/TSVs .
  • Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.
  • Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.
  • Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .
  • Hands on experience on industry standard tools used for DFT features
  • Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.
  • Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.
  • Excellent analytical and problem-solving skills, with a keen attention to detail.
  • Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams

  • Preferred technical and professional experience
  • Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design
  • Experience working with ATE engineers for silicon bring up, silicon debug and validation.
  • Experience in Asics/processor flow and post silicon validation
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