Staff Engineer, Systems Design Engineering

Position Overview:

We are seeking an experienced Principal System Design Engineer to join our dynamic engineering team. This position offers the opportunity to work on next generation NAND Flash Storage systems, develop solutions demonstrating cutting-edge architecture and extreme performance, and contribute to the validation and verification of complex designs. The ideal candidate will bring 7-10 years of proven experience in FPGA design, RTL development, and embedded systems, combined with a solid foundation in digital design principles.

Role:

You will lead sophisticated FPGA implementations, architect high-performance IP solutions, and drive innovation in accelerated, adaptive computing while collaborating with cross-functional teams to deliver industry-leading storage solutions. You will develop critical RTL logic, be responsible for porting RTL for FPGA implementation, and oversee the verification and validation of FPGA designs to ensure robust, production-ready solutions.

Key Responsibilities:

FPGA Design & Development:

• Design, implement, and optimize complex digital systems using Xilinx FPGAs (Zynq, UltraScale+, Versal architectures)

• Develop and maintain RTL code using VHDL/Verilog for high-speed digital signal processing applications

• Create timing-critical designs meeting stringent performance requirements

• Implement advanced FPGA features including DSP blocks, block RAM, and high-speed transceivers

RTL IP Design & Integration:

• Design reusable, parameterizable IP cores for various applications

• Develop custom interfaces including PCIe, AXI4, DDR memory controllers, and high-speed serial protocols

• Create comprehensive IP documentation and integration guidelines

• Collaborate with IP verification teams to ensure robust, production-ready designs

Embedded Firmware Development:

• Develop embedded software for Zynq SoCs and microprocessor systems

• Implement device drivers and low-level firmware for FPGA-CPU interfaces

• Optimize software-hardware partitioning for maximum system performance

• Work with real-time operating systems and bare-metal implementations

System Debug & Validation:

• Lead comprehensive FPGA system validation and verification efforts

• Develop and execute test plans for complex digital systems

• Utilize advanced debug tools including ChipScope, ILA, and hardware debuggers

• Perform signal integrity analysis and timing closure activities

• Troubleshoot complex hardware-software integration issues

Technical Leadership:

• Mentor junior engineers and provide technical guidance on FPGA best practices

• Participate in design reviews and architectural decisions

• Interface with customers and stakeholders on technical requirements

• Drive continuous improvement in design methodologies and tools Qualifications

Experience & Technical Skills:

• 5-7 years of proven experience in FPGA design and development

• Extensive hands-on experience with Xilinx FPGAs, including:

• Zynq-7000 and Zynq UltraScale+ SoCs

• Vivado Design Suite and associated tools

• IP Integrator and block design methodologies

• Strong RTL design skills with VHDL/Verilog

• Embedded firmware development experience with C/C++ for ARM Cortex processors

• System-level debug and validation expertise using industry-standard tools

• Experience with high-speed interfaces (PCIe, DDR3/4 and NAND Flash)

Core Competencies:

• Strong problem-solving and analytical skills

• Ability to multi-task and meet deadlines.

• Ability to work collaboratively in cross-functional teams

• Excellent communication (written and verbal) and interpersonal skills.

• Familiarity with version control systems (Git, SVN)

• Knowledge of scripting languages (Python, Tcl, Bash)

Education & Certifications:

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field

Preferred Qualifications:

• Machine learning principles and implementation on FPGA platforms

• Experience with other FPGA vendors (Intel/Altera, Microsemi, Lattice)

• Knowledge of AI acceleration frameworks and neural network deployment

• Familiarity with high-level synthesis (HLS) for ML workloads

• Experience with high-level synthesis tools (HLS)