We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: - has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. - has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints - has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. - Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements - Independent, timely decision maker and able to cope with interrupts - Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 8+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required.

"> Search Jobs Find Jobs For Where Search Jobs Analog Design, Staff Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 5365 Remote Eligible No Date Posted 23/08/2024 Qualifications: Key Qualifications: Btech/Mtech with 4 -10 years of SerDes/High-Speed analog design experience. Experience in design of Analog front-end transceivers, voltage/current-mode drivers , delay-locked loop, phase-locked loop, Regulators, Equalizers (CTLE, FFE, DFE), Impedance calibrators, serializer , De-serializers , voltage-controlled oscillator, phase interpolator, bandgap reference, Clock data recovery circuits, Injection locked Loop etc. Hands ON experience with spice simulations and various sub-micron design methodologies. Familiarity with automation / Scripting language(TCL, PERL). Silicon-proven experience implementing circuits for analog and mixed-signal building blocks. Can micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit. Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). JOB Responsibilities Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Collaborate with digital RTL engineers on the verification of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Analyze various analog circuit techniques for dynamic and static power reduction, performance enhancement, and area reduction. Develop Analog Full custom circuit macros, including Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, and Analog Front End needed for High-Speed PHY IP. Leverage your understanding of circuit design and layout, along with knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. Collaborate with experienced teams locally and globally to deliver high-performance silicon chips. Create simulation environments to verify circuit specifications and debug circuits as needed. Optimize layouts and parasitics to enhance circuit performance and reliability. The Impact You Will Have: Contribute to the design and verification of advanced silicon chips, accelerating their development and manufacturing processes. Enable customers to optimize their chips for power, cost, and performance, significantly reducing project schedules. Drive innovations in high-speed physical interfaces, enhancing the performance and reliability of our products. Collaborate with global teams to leverage diverse expertise and deliver cutting-edge technology solutions. Influence the development of next-generation processes and models for manufacturing high-performance silicon chips. Ensure the successful implementation of analog and mixed-signal circuit designs in advanced CMOS technologies. What You ll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical/Electronics/VLSI Engineering or a related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron design methodologies. Experience with analog transistor-level circuit design in nanometer technologies. Familiarity with Multi Gbps range high-speed designs, including PAM4 serdes architectures. Proficiency in creating simulation environments and debugging circuits. Who You Are: Detail-oriented with excellent problem-solving skills. Strong communicator, capable of collaborating with teams across different locations. Innovative thinker with a passion for technology and circuit design. Proactive and self-motivated, with the ability to work independently and as part of a team. Adaptable and open to learning new techniques and methodologies.

We are seeking a highly motivated and experienced Digital Design Manager to lead a team of seasoned digital design engineers. You possess a deep understanding of the ASIC digital design flow, along with hands-on experience in HDL coding, RTL2GDSII flow, and scripting languages. You excel in managing project execution from defining specifications to silicon validation and characterization. Your leadership skills foster a collaborative environment, driving your team to meet stringent project requirements and deliver superior quality designs. With a minimum of 10 years in digital design and at least 3 years in a managerial role, you bring a wealth of knowledge and a proven track record of successful project completions. What You ll Be Doing: Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements. Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs. Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools. Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods. Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off. Support silicon validation and characterization through test chip implementation. Manage team members and operations, including career development and planning. The Impact You Will Have: Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys product offerings. Ensure high-quality and robust designs that meet customer requirements and improve system performance. Streamline the digital design process from specification to silicon validation, reducing time-to-market. Lead a team of talented engineers, fostering a collaborative and productive work environment. Contribute to the continuous improvement of design methodologies and best practices. Support Synopsys position as a leader in the semiconductor industry through successful project deliveries. What You ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow. Working knowledge of scripting languages like Perl, Shell, Python, and Tcl. Experience in leading a small team of digital design engineers to execute projects. Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable. Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging. Familiarity with Synopsys toolset is highly desirable. Minimum 10 years of relevant digital design experience with at least 3 years as a people manager. B.E/B.Tech/M.Tech in ECE/EE. Who You Are: Strong leadership skills with a proven track record of managing and developing teams. Excellent problem-solving abilities and attention to detail. Effective communication skills, both written and verbal. Ability to work collaboratively in a fast-paced, dynamic environment. Innovative and proactive mindset with a passion for continuous improvement

Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively

Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

Enable, support, and debug transistor-level flows and processes. Design, develop, troubleshoot, and debug software tools and flows for the development of integrated circuits. Support a global design team, debug CAD issues, interface with foundries, configure the CAD environment, and design flows. Develop routines and utility programs to aid in the design of integrated circuits. Build productive internal and external working relationships. Requirements: A relevant degree in electronic/microelectronic engineering. 5+ years of relevant experience. Strong desire to learn and explore new technologies, demonstrating good analysis and problem-solving skills. Ability to exercise judgment within defined procedures and practices to determine appropriate action. Good knowledge of hardware integrated circuits. UNIX/Linux user knowledge. Proficiency with at least one programming language. Proficiency with scripting languages to automate processes. Good English communication skills. Capability to produce adequate technical documentation. Preferred Qualifications: Experience with the VLSI domain, including familiarity with DRC/LVS extraction, simulation, and EMIR. Experience with Cadence, Custom Designer EDA tools. Experience in data management and job scheduling tools like LSF/GRID Engine. Experience in Python, TCL, or Shell scripting. IC design experience (analog or digital).

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Staff Engineer Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 7227 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated individual with a strong background in Electronics and Communication Engineering or Computer Science. You have a keen interest in software development and system validation, and you are eager to apply your skills in a dynamic and innovative environment. You thrive on solving complex problems and are always ready to take on new challenges. Your technical prowess is complemented by your excellent communication skills, making you an effective team player and a valuable contributor to any project. You have a meticulous eye for detail and a commitment to delivering high-quality work. You are not only technically proficient but also adaptable, able to quickly learn new tools and methodologies. Your previous experience in embedded systems, board-level testing, and programming in C/C++ sets you apart, and you are excited about the opportunity to work with high-speed serial interfaces and FPGA-based setups. Your proactive approach and analytical mindset enable you to excel in a fast-paced, collaborative environment. What You ll Be Doing: Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You ll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills. Who You Are: A proactive and motivated individual with a passion for technology and innovation. An effective communicator who can articulate technical concepts clearly and concisely. A team player who collaborates well with others and contributes to collective goals. A detail-oriented professional with a strong analytical mindset. An adaptable learner who thrives in dynamic environments and embraces new challenges. The Team You ll Be A Part Of: You will be part of a dedicated team focused on the development and validation of high-speed serial interfaces and embedded systems. The team collaborates closely to ensure the quality and performance of Synopsys products, leveraging a diverse set of skills and expertise. You will work alongside experienced engineers who are passionate about technology and committed to driving innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

Lead the team developing high-performance instruction accurate models of RISC-V, RH850, TriCore and Arm CPUs and System Level IP models Develop Virtual Platforms for testing Integrate instruction accurate models and platforms from Synopsys partners Contribute to the continuous improvement of Synopsys modelling methodologies. Configure and bring up complex software stacks and drivers on the simulated hardware Work closely with other development teams, 3rd party suppliers, support engineers and customers to identify, implement and deliver solutions Interact with Synopsys development teams working on other modelling technologies, advanced architectures, hardware design, software design, and validation Key Requirements/Qualifications: Good programming skills in C and C++ Scripting Languages, preferably Python Excellent communication and problem-solving skills University degree (min. B.E/B/Tech or M.Tech) in Computer Science / Electronics or similar with 12+ years industry experience Useful to Have: Understanding of CPU architecture and familiarity with one or more CPU instruction sets Experience with RISC-V/RH850/Arm CPUs and/or knowledge of RISC-V/RH850/Arm architecture is an advantage Embedded knowledge, and ability to interpret H/W device specifications Knowledge of System Architectures including OS kernel internals SystemC and transaction-level modelling knowledge would be beneficial but not essential, as would familiarity with high performance modeling (Dynamic Binary Translation (DBT), Just In Time (JIT) code morphing)

You are a passionate and detail-oriented engineer with a deep understanding of Static Timing Analysis (STA). You thrive in a collaborative environment, working closely with cross-functional teams to solve complex technical challenges. Your expertise in Synopsys PrimeTime and related technologies allows you to diagnose issues and propose innovative solutions that enhance product quality. You are self-motivated, with a proven track record of executing comprehensive validation plans and delivering high-quality results. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python enable you to streamline processes and improve efficiency. You are committed to continuous learning and staying up-to-date with the latest industry trends and advancements. What You ll Be Doing: Execute and lead product validation of Synopsyss PrimeTime tool by understanding requirements specifications and functional specifications, customer use cases. Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to reduce customer incoming thereby improving product quality. Collaborate with cross-functional teams such as R&D, Product Engineering, Field and Customers, recommend improvements in implementation and validation. Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues and propose solutions to ensure quality and readiness of the product/solution for customer deployment. Demonstrate a high level of attention to detail and accuracy in all tasks. Perform risk assessments and develop mitigation strategies to address potential product validation issues. Analyze validation data to identify trends, discrepancies and areas for improvement. Prepare detailed validation reports to present to multi-functional teams and management. The Impact You Will Have: Ensure the high quality and reliability of Synopsyss PrimeTime tool, contributing to its success in the market. Enhance customer satisfaction by proactively identifying and addressing potential issues before they impact users. Collaborate with R&D and Product Engineering teams to drive continuous improvements in product design and functionality. Provide valuable insights and recommendations that influence the development and validation of future product releases. Contribute to the overall success of Synopsys by ensuring that our tools meet the highest standards of performance and reliability. Support the deployment of cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. What You ll Need: Deep domain knowledge in Static Timing Analysis. BSEE or equivalent and a minimum of 2 years of related experience or MSEE or equivalent and a minimum of 1 year of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, Extraction, power, SDC constraints, advanced OCV concepts, derates, PBA timing, distributes, hierarchical STA flows, and/or physical design closure. Exceptional debugging skills. Proficient in software and scripting skills (Perl, Tcl, Python). Detail-oriented with a focus on maintaining high standards of product quality. Who You Are: Collaborative team player with excellent communication skills. Analytical thinker with a problem-solving mindset. Proactive and self-motivated individual. Adaptable and flexible in a fast-paced environment. Strong attention to detail and accuracy.

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol * Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification.

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design. You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structure, and interconnect failure modes in advanced finfet technology nodes. You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology. You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation. You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution. What you'll Be Doing: Leading Serdes analog design and development. Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What you'll Need: BE 18+ years of relevant experience or MTech 15+ years of relevant experience in mixed signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Strong fundamentals of CMOS, device physics, and sub-micron design methodologies. Experience with PLL designs and high-speed digital circuit design. Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experience in LC VCO/DCO design and performance parameters of VCO. Familiarity with digitally assisted analog circuit techniques. The Team you'll Be A Part Of: You will be joining an expanding analog/mixed-signal serdes team involved in the design and development of cutting-edge High Speed PHYSICAL Interface Development. You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

"> Search Jobs Find Jobs For Where Search Jobs IP Firmware Development, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 9264 Remote Eligible No Date Posted 20/03/2025 non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Sr Staff Engineer (VIP verification) Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 8839 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 7yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs ASIC Digital Design Engineer, Senior Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 8686 Remote Eligible No Date Posted 28/01/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You ll Be Doing: Developing and verifying digital designs for next-generation NRZ and PAM-based SerDes products. Running lint/cdc/rdc checks and synthesis flow. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience with Verilog and VCS. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a strong background in C++ programming and software design. With your expertise in data structures and algorithms, you can tackle complex problems efficiently and optimize existing solutions. Your proficiency in scripting languages like Python, Shell, and Perl allows you to automate tasks and streamline processes, making you an invaluable asset in a fast-paced development environment. Your experience with ML/AI technologies is essential, as you will be enhancing operations projects with these advanced techniques. You thrive in collaborative settings, working seamlessly with cross-functional teams to develop, maintain, and optimize software solutions. Your solid understanding of Linux environments enables you to troubleshoot and resolve software-related issues effectively. You possess excellent problem-solving and analytical skills, coupled with strong communication and collaboration abilities. You are adaptable and capable of working in a dynamic team environment, always eager to learn and contribute to the team's vision and product success. What Youll Be Doing: * Designing, coding, and testing software components with proficiency in C++ programming. * Creating and maintaining Makefiles, BOM files, and build systems to streamline the software build and deployment process. * Utilizing scripting languages such as Python, Shell, and Perl for automation, testing, and system-level tasks. * Applying ML/AI technologies to enhance operations projects and develop sophisticated algorithms. * Collaborating with cross-functional teams throughout the software development lifecycle, from concept to deployment. * Troubleshooting and resolving software-related issues in a Linux environment. The Impact You Will Have: * Contributing to the development and enhancement of cutting-edge software applications. * Improving the efficiency and reliability of software build and deployment processes. * Automating repetitive tasks and optimizing system-level operations. * Enhancing the capabilities of operations projects with advanced ML/AI technologies. * Ensuring seamless collaboration and communication within cross-functional teams. * Resolving complex software issues and contributing to a robust and reliable software environment. What You’ll Need: * Bachelor's or Master's degree in Computer Science, Software Engineering, or a related field. * 2-6 years of relevant experience in software development and R&D projects. * Strong proficiency in C++ programming and software design. * Experience with data structures and algorithms. * Knowledge of version control systems (Perforce, Git, SVN). * Familiarity with Makefiles and build systems. * Proficiency in scripting languages like Python, Shell, and Perl. * ML/AI experience is essential. * Solid understanding of Linux environments. Who You Are: You are a detail-oriented and innovative thinker with a passion for technology and software development. Your excellent problem-solving skills and analytical mindset allow you to tackle challenges creatively and efficiently. You have strong communication and collaboration abilities, making you an effective team player who can work seamlessly with others. You are adaptable, eager to learn, and driven to contribute to the success of the team and the company. The Team You’ll Be A Part Of: You will be joining a dynamic and innovative R&D team dedicated to developing cutting-edge software solutions. Our team is focused on continuous improvement, leveraging the latest technologies to enhance our products and processes. Collaboration is at the heart of what we do, and we work closely with cross-functional teams to achieve our goals and drive technological advancements.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team, What Youll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs, Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements, Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, Developing verification plans and driving functional coverage-driven verification closure of real designs, Debugging and resolving issues in verification environments to ensure robust and reliable verification processes, The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes, Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols, Driving innovation in the automotive sector by developing robust verification solutions for automotive systems, Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices, Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements, Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products, What Youll Need: E/B Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs, Proficiency in writing scripts using Perl, Python, and Shell scripting, Who You Are: Excellent problem-solving, debugging, and analytical skills, Strong programming skills and familiarity with object-oriented programming concepts, Creative and innovative mindset, Excellent verbal and written communication skills, A collaborative team player with a passion for functional verification,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team, What Youll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs, Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements, Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, Developing verification plans and driving functional coverage-driven verification closure of real designs, Debugging and resolving issues in verification environments to ensure robust and reliable verification processes, The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes, Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols, Driving innovation in the automotive sector by developing robust verification solutions for automotive systems, Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices, Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements, Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products, What Youll Need: E/B Hands-on experience in architecting and building System Verilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience with Display Port/HDMI/MIPI/USB/PCI-E protocol preferably the latest specifications Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs, Proficiency in writing scripts using Perl, Python, and Shell scripting, Who You Are: Excellent problem-solving, debugging, and analytical skills, Strong programming skills and familiarity with object-oriented programming concepts, Creative and innovative mindset, Excellent verbal and written communication skills, A collaborative team player with a passion for functional verification,