Senior Manager, Processor Modeling R&D

Lead the team developing high-performance instruction accurate models of RISC-V, RH850, TriCore and Arm CPUs and System Level IP models Develop Virtual Platforms for testing Integrate instruction accurate models and platforms from Synopsys partners Contribute to the continuous improvement of Synopsys modelling methodologies. Configure and bring up complex software stacks and drivers on the simulated hardware Work closely with other development teams, 3rd party suppliers, support engineers and customers to identify, implement and deliver solutions Interact with Synopsys development teams working on other modelling technologies, advanced architectures, hardware design, software design, and validation Key Requirements/Qualifications: Good programming skills in C and C++ Scripting Languages, preferably Python Excellent communication and problem-solving skills University degree (min. B.E/B/Tech or M.Tech) in Computer Science / Electronics or similar with 12+ years industry experience Useful to Have: Understanding of CPU architecture and familiarity with one or more CPU instruction sets Experience with RISC-V/RH850/Arm CPUs and/or knowledge of RISC-V/RH850/Arm architecture is an advantage Embedded knowledge, and ability to interpret H/W device specifications Knowledge of System Architectures including OS kernel internals SystemC and transaction-level modelling knowledge would be beneficial but not essential, as would familiarity with high performance modeling (Dynamic Binary Translation (DBT), Just In Time (JIT) code morphing)