Job
Description
An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design. You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structure, and interconnect failure modes in advanced finfet technology nodes. You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology. You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation. You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution. What you'll Be Doing: Leading Serdes analog design and development. Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What you'll Need: BE 18+ years of relevant experience or MTech 15+ years of relevant experience in mixed signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Strong fundamentals of CMOS, device physics, and sub-micron design methodologies. Experience with PLL designs and high-speed digital circuit design. Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experience in LC VCO/DCO design and performance parameters of VCO. Familiarity with digitally assisted analog circuit techniques. The Team you'll Be A Part Of: You will be joining an expanding analog/mixed-signal serdes team involved in the design and development of cutting-edge High Speed PHYSICAL Interface Development. You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.
