Staff SoC Design Engineer

Staff SoC Design Engineer

Company Description

Location: Hyderabad

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 60 employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. If you have this type of passion, we invite you to apply for this job.

ASIC/SoC Design position is your opportunity to join one of the industry's leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture. As the ASIC/SoC Design Engineer for Axiado, you will have the opportunity to work in all areas of the SoC design flow. You will work closely with the Architecture, Verification, Physical Design and Software teams, and report to the Director of Engineering.

KEY RESPONSIBILITIES

• Help develop the design and implementation of SoCs.

• Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;

• Top-level and block-level performance, bandwidth, and power optimization;

• Work with FPGA engineers to perform early prototyping; and

• Support test program development, chip validation, and chip life until production maturity.

• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Qualifications

• 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization;

• Proficient in writing clear, implementable micro-architecture specifications;

• Expertise in writing efficient RTL code in Verilog and SoC integration

• Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure;

• Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.

• Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.

• Fluency with scripting languages (e.g., Perl, Python);

• Must have gone through at least one tapeout.

• Preferred: Silicon bring-up and debug experience

• Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.

Sunaina Arora

Talent Acquisition

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