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Alphawave Semi
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Staff Engineer I - DFT

Staff Engineer I - DFT

Alphawave Semi

8 - 13 years

5 - 9 Lacs

bengaluru

Posted:2 months ago| Platform:

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Skills Required

wireless automation vhdl dft networking soc verilog perl medical insurance python

Work Mode

Work from Office

Job Type

Full Time

Job Description

As a DFT engineer at Alphawave Semi, you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and Alphawave specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. You will collaborate closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams.

What youll do :

Acting as a member of Alphawave central DFT methodology group responsible for developing, maintaining and supporting flows across all company business units and projects
Architecting methodologies and flows for an integrated, RTL centric "shift left" DFT environment across company IPs, ASICs and SoC designs.
Writing and automating RTL for advanced DFT and DFD features not currently supported by the EDA vendors
Developing automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification.
Building IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures. Creating automated QoR checks for implementation quality control.
Writing static timing constraints, creating waivers and devising flows for bullet proof timing checks

What youll need:

Bachelors degree in engineering science, Electrical and Computer Engineering or Computer Science
8+ years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles.
Vast experience with various DFT EDA tools from Siemens, SNPS and Cadence
Good knowledge and understanding in Verilog/VHDL and SystemVerilog
Exposure to CAD and automation. Good exposure for using de-Perl techniques in creating generic codes. Knowledge of TCL and Python is a plus.
Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs is highly desirable.
Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.

We have a flexible work environment to support and help employees thrive in personal and professional capacities "

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

Competitive Compensation Package
Restricted Stock Units (RSUs)
Provisions to pursue advanced education from Premium Institute, eLearning content providers
Medical Insurance and a cohort of Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility

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Staff Engineer I - DFT