Posted:2 days ago|
Platform:
Work from Office
Full Time
Job Description
Handling block layouts like Charge Pumps, I/O s, Reference generators
Involve in the full chip Signal/Power planning, die size estimation.
Interact with project lead (design and layout) and CAD for various requirements
Work with the project lead on chip level integration task and tape out procedures
Schedule planning of the assigned task.
Person will be working with our India and US physical design teams for all tasks.
Mentor junior team members
Qualifications
BE/ME/BTECH/MTECH/MS with relevant 4-8 years Engineering experience
Qualifications
Experience in Cadence Platform
Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM
PDK and rule-set development understanding
Full chip development and tape out flow
Working experience in blocks like high speed IO, Charge pumps, Regulators, semi-custom blocks etc.
Scripting knowledge a plus: PERL and SKILL
Good communication (written and verbal) and interpersonal skills
Excellent working ability with circuit design and layout methodology development teams
Excellent problem-solving skills
Western Digital
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.
We have sent an OTP to your contact. Please enter it below to verify.
Instantly access job listings, apply easily, and track applications.
15.0 - 19.0 Lacs P.A.
Bengaluru, Karnataka, India
Salary: Not disclosed
Bengaluru
9.0 - 14.0 Lacs P.A.
15.0 - 22.5 Lacs P.A.
40.0 - 70.0 Lacs P.A.
16.0 - 18.0 Lacs P.A.
Bengaluru
12.0 - 17.0 Lacs P.A.
Bengaluru
50.0 - 100.0 Lacs P.A.
8.0 - 10.0 Lacs P.A.
Chennai
18.0 - 20.0 Lacs P.A.
