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ARM Embedded Technologies
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Staff Design Constraints Engineer

Staff Design Constraints Engineer

ARM Embedded Technologies

8 - 13 years

30 - 35 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

sta timing closure formal verification soc front end design perl arm electronics engineering python recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

Responsibilities

As a creative Design Constraints Engineer, you will be part of the Front-End Design team, developing, validating , optimizing , and handing off constraints for complex SoCs, ensuring robust timing closure and seamless integration across the various stages of SOC design cycle.

Your key responsibilities will include creating and maintaining Design constraints, validating them using industry standard STA tools and handing off to the Implementation teams.

You will closely work with the Design team to capture the Design constraints.

You will be validating these constraints using industry standard constraint validation tools like Time Vision and other equivalent tools.

You will partner with the Implementation teams to resolve timing and constraint-related issues .

You will also contribute to developing and enhancing the design methodologies used by the team.

You will guide and support other members of the team as needed to enable the successful completion of project activities.

Required Skills and Experience:

Bachelor s or master s degree on Electrical & Electronics Engineering, VLSI or an equivalent discipline.

Experience of 8+ years working in Design, Synthesis and Design constraints of complex Subsystems or SoCs

Strong expertise in SDC syntax and timing constraint methodologies

Expertise in Constraints development and validation tools such as Time Vision, or any equivalent

Proficient in STA tools such as Synopsys PrimeTime , Cadence Tempus, or equivalent

Experience in synthesis tools (Design Compiler, Genus) and PnR tools (ICC2, Innovus) preferred

Familiarity with multi-mode multi-corner (MMMC) timing closure

Proficient in Perl, Python, Tcl or other scripting language

Good communication (written, verbal, presentations) skills.

Desired Skills and Experience:

Experience leading Synthesis and Design constraints for Subsystems or SoCs

Knowledge of clock-domain crossing (CDC) and asynchronous design constraints

Familiarity with formal verification of constraints.

Exposure to high-speed interface constraints (DDR, PCIe, etc.).

Knowledge of DFT and Physical Implementation

Experience with ARM-based designs and/or ARM System Architectures

Equal Opportunities at Arm

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