Senior Verification Engineer

What you will do

• Work under broad guidance and create verification plan based on the IP design specification
• Build Standalone IP test bench using System Verilog
• Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC)
• Use the IP/SOC RTL in system Verilog based logic verification environment & complete the functional verification
• Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality.
• Deliver the functional test vectors needed to be used for post-silicon validation.
• Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase

Who you are and what you bring

• Fair understanding and experience of logic verification environment (UVM & System Verilog)
• Fair understanding of ARM microcontroller (Preference Cortex M4) architecture & debug infrastructure
• Hands on experience one/as many of the following silicon Ips (UART, CAN-FD, I2C, SPI, QSPI, SD/UMMC, General purpose timer/pulse width modulator etc...)
• Hands on experience in functional verification of ARM Cortex M4 based Subsystem/SOC verification, including debug interfaces like SWD & SWJ.
• Awareness of Cryptography algorithms, data encryption/decryption verification will be a significant added advantage
• Ability to quickly adapt to other categories of C-based/System Verilog based IP verification
• Experience and ability to bring complex SOCs into the physical world and into production.
• Excellent problem-solving skills, written & verbal communication skills
• #Logic Verification #Embedded C Verification #ARM #Boot.
• Prior hands-on work experience of at least 4 years in Logic IP Verification based on System Verilog.