Senior Staff Verification Engineer Talent21 Management Shared Services Pvt. ltd.

5.0 - 10.0 years

6 - 10 Lacs

bengaluru

Work from Office

What you will do Work on creating verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all control...

Posted 18 hours ago

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Staff Verification Engineer Talent21 Management Shared Services Pvt. ltd.

6.0 - 11.0 years

10 - 20 Lacs

bengaluru

Work from Office

What you will do Work on creating verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/ SOC RTL in system verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all contro...

Posted 18 hours ago

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Senior Verification Engineer Talent21 Management Shared Services Pvt. ltd.

4.0 - 8.0 years

5 - 9 Lacs

bengaluru

Work from Office

What you will do Work under broad guidance and create verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system Verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tap...

Posted 18 hours ago

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