7 Logic Verification Jobs

Key Responsibilities: Responsible for maintenance, calibration, and troubleshooting of field instruments (pressure, temperature, flow, level, analyzers, etc.). Ensure reliable operation of control systems including DCS and PLC. Perform loop checking, logic verification, and preventive maintenance of instrumentation systems. Read and interpret technical documents such as P&IDs, loop drawings, wiring diagrams, and logic diagrams. Coordinate with operations and electrical teams to ensure minimum downtime and optimal process performance. Maintain documentation of calibration

What you will do Work under broad guidance and create verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system Verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tap...

What you will do Work on creating verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/ SOC RTL in system verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all contro...

What you will do Work on creating verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all control...

What you will do Work on creating verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all control...

What you will do Work on creating verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/ SOC RTL in system verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all contro...

What you will do Work under broad guidance and create verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system Verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tap...