Senior Verification Engineer

As a Verification Engineer at our leading international semiconductor team, you will play a crucial role in ensuring the functionality, performance, and quality of advanced chip designs at the block, subsystem, and top levels. Key Responsibilities: - Develop and execute verification plans utilizing SystemVerilog and UVM - Perform verification at block, subsystem, and top levels - Implement formal and dynamic verification methods - Drive regression testing and automation through scripting languages - Collaborate closely with design teams to tackle complex verification challenges - Utilize version control and industry-standard verification methodologies Requirements: - Masters or PhD in Electronics, Computer Science, or a related field - Minimum 8 years of industrial experience in verification - Proficiency in SystemVerilog and UVM - Strong knowledge of simulation methodologies and tools - Hands-on experience with scripting languages such as Python, Perl, Bash, TCL - Familiarity with regression tools and version control systems like git, svn - Proven expertise in formal and dynamic verification - Strong problem-solving skills and attention to detail - Excellent teamwork and communication abilities Join us for the opportunity to work on cutting-edge semiconductor projects and advance your career in semiconductor verification. Apply now by sending your resume to hr@geesesquads.com.,