Senior Staff To Principal Design Verification Engineer

Your Team, Your Impact

What You Can Expect

• Develop and maintain verification plans in alignment with architectural and design requirements.
• Architect and implement advanced simulation test benches to validate DUT functionality.
• Design and execute both directed and constrained-random test scenarios.
• Collect, analyze, and improve code and functional coverage metrics.
• Perform root-cause analysis and debug failures in simulation, DUT, or test cases.
• Utilize UVM or equivalent methodologies for system-level verification.
• Collaborate with hardware and firmware teams to ensure cohesive integration and debugging.
• Participate in continuous improvement of verification processes, tools, and methodologies

What Were Looking For

• Bachelor s or Master s degree in Computer Science, Electrical Engineering with 8+ years of experience in Digital Pre-Silicon Verification.
• Strong proficiency in SystemVerilog and HDL languages. Hands-on experience with UVM or other industry-standard verification methodologies.
• Experience in Subsystem and SoC verification
• Ability to write and interpret architectural/design specifications and verification requirements.
• Experience in writing verification test plans.
• Proficiency in developing complex simulation test benches.
• Ability to implement directed and constrained-random test cases.
• Experience with functional and code coverage collection, analysis, and closure.
• Strong debugging skills for simulation issues, test cases, tools, and DUT (Device Under Test).
• Familiarity with ARM M series Processors and assembly language.
• Proficiency in scripting languages such as Perl, Shell, and Python.