Senior IP Design Verification (Embedded Processor)

5 - 10 years

0 Lacs

Posted:1 week ago| Platform: Shine logo

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On-site

Job Type

Full Time

Job Description

As part of the Embedded Processors group of TI, you will be working with the Processors and Application Specific Microcontroller (ASM) Business Units. Your role will involve developing cutting-edge system-on-chips (SoCs) for microcontrollers and processors, including 5nm technologies, for industrial and automotive applications. The team is known for creating differentiated IPs with patented technologies that enhance ADAS, Zonal, Domain controller, and Real-Time Control application performance. Your responsibilities will include designing high-performance CPU cores, math co-processors, interconnects, networking and multimedia controllers, safety and security infrastructure, and control and communication peripherals. **Responsibilities:** - Drive verification strategy, create Test Plans, and develop Test Benches for IPs - Own IP DV signoff using SV & UVM or Formal Verification - Develop UVM components like agents, drivers, monitors, and scoreboards - Implement Formal Property modeling, Assertions, and Covers - Efficiently develop test cases - Define and achieve all functional coverage goals - Ensure 100% code coverage (Block, expression, FSM) in IP DV - Implement continuous improvements using the latest methodologies/technologies **Mini Qualifications:** - Bachelors/Masters in EE/EC/VLSI stream with 5-10 years of relevant experience in IPDV - Strong knowledge in System Verilog/UVM - Experience in Assertion Based Formal Property verification is preferred - Proficiency in HDLs like Verilog/VHDL/SV - Strong scripting skills with Perl/Tcl/Python - Excellent debugging and problem-solving skills - Effective communication skills to interact with all stakeholders - Knowledge of standard protocols like AHB, AXI, APB, CAN, Ethernet, I2C, SPI, UART - Knowledge of ARM processors is a plus In addition, experience in IP DV, SoC DV, and post-silicon debug as well as familiarity with Cadence tools (IES, IEV/Jasper Gold) will be advantageous.,

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