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Senior Engineer Digital Functional Verification

3 - 8 years

5 - 10 Lacs

Bengaluru

Posted:2 weeks ago| Platform: Naukri logo

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Skills Required

Computer science RTL design VHDL Semiconductor formal verification Diversity and Inclusion System verilog Firmware UVM IPS

Work Mode

Work from Office

Job Type

Full Time

Job Description

Develop verification environments for our ICs using Universal Verification Methodology (UVM); Job Description In your new role you will: create and define verification plans; develop verification environments for our ICs using Universal Verification Methodology (UVM); draw on test scenarios using SystemVerilog; verify functionality using the Constrained Random approach; develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies; provide proactive support to users of our verification flowenvironment; be responsible for our verification methods; Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least 3 years of experience in Constrained-Random Metric-Driven Verification You have capabilities and experience in working withmicrocontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog; Have knowledge of firmware and RTL design (VHDL); Ideally have knowledge of working with Verification IPs (VIPs) Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.

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