Senior Digital Verification Engineer

Job Description

You are an experienced ASIC Digital Design Engineer with a deep understanding of interface protocols such as USB2/3/3.1, PCIe Gen1/2/3/4/5/6, Ethernet, and JESD204B. With a solid background in SERDES/PHY/Controller IP specification and compliance validation, you thrive in dynamic environments where your expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM) is highly valued. You are passionate about delivering high-quality RTL and simulation models, and you excel in developing and reviewing verification plans and environments. Your proactive approach to problem-solving, coupled with your ability to support customers during silicon bring-up and debug phases, makes you an invaluable asset to any team. Your technical prowess is matched by your excellent communication skills, enabling you to effectively collaborate and influence across departments and with external partners. What You'll Be Doing: Developing and reviewing verification plans for SERDES/PHY/Controller IPs. Creating and maintaining verification environments, with a preference for UVM. Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure. Delivering high-quality RTL and simulation models to customers. Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems. Supporting customers with IP integration, silicon bring-up, and debugging issues. Demonstrating Testchip+FPGA system demos to customers and at conferences. The Impact You Will Have: Ensuring the compliance and functionality of our interface IPs with industry protocols. Enhancing the quality and reliability of our silicon solutions for customers. Facilitating smooth customer adoption and integration of our IPs. Contributing to successful silicon bring-up and debugging efforts. Showcasing our technological advancements at industry events. Driving innovation and excellence in digital design and verification processes. What You'll Need: Expertise in one or more interface protocols (e.g., USB, PCIe, Ethernet, JESD204B). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Experience with SERDES/PHY/Controller IP specification and compliance validation. Strong background in developing and reviewing verification plans and environments. Ability to deliver high-quality RTL and simulation models to customers.